void recalibrate_iodelay(void) { struct pad_conf_entry const *pads, *delta_pads = NULL; struct iodelay_cfg_entry const *iodelay; int npads, niodelays, delta_npads = 0; int ret; switch (omap_revision()) { case DRA722_ES1_0: case DRA722_ES2_0: pads = dra72x_core_padconf_array_common; npads = ARRAY_SIZE(dra72x_core_padconf_array_common); if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); iodelay = dra72_iodelay_cfg_array_revc; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); } else { delta_pads = dra72x_rgmii_padconf_array_revb; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); iodelay = dra72_iodelay_cfg_array_revb; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); } break; case DRA752_ES1_0: case DRA752_ES1_1: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; default: case DRA752_ES2_0: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); /* Setup port1 and port2 for rgmii with 'no-id' mode */ clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | RGMII1_ID_MODE_N_MASK); break; } /* Setup I/O isolation */ ret = __recalibrate_iodelay_start(); if (ret) goto err; /* Do the muxing here */ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); /* Now do the weird minor deltas that should be safe */ if (delta_npads) do_set_mux32((*ctrl)->control_padconf_core_base, delta_pads, delta_npads); /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); err: /* Closeup.. remove isolation */ __recalibrate_iodelay_end(ret); }
void recalibrate_iodelay(void) { struct pad_conf_entry const *pads, *delta_pads = NULL; struct iodelay_cfg_entry const *iodelay; int npads, niodelays, delta_npads = 0; int ret; switch (omap_revision()) { case DRA722_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: pads = dra72x_core_padconf_array_common; npads = ARRAY_SIZE(dra72x_core_padconf_array_common); if (board_is_dra71x_evm()) { pads = dra71x_core_padconf_array; npads = ARRAY_SIZE(dra71x_core_padconf_array); iodelay = dra71_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); /* If SW8 on the EVM is set to enable NAND then * overwrite the pins used by VOUT3 with NAND. */ if (!nand_sw_detect()) { delta_pads = dra71x_nand_padconf_array; delta_npads = ARRAY_SIZE(dra71x_nand_padconf_array); } else { delta_pads = dra71x_vout3_padconf_array; delta_npads = ARRAY_SIZE(dra71x_vout3_padconf_array); } } else if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); iodelay = dra72_iodelay_cfg_array_revc; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); } else { delta_pads = dra72x_rgmii_padconf_array_revb; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); iodelay = dra72_iodelay_cfg_array_revb; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); } break; case DRA752_ES1_0: case DRA752_ES1_1: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; case DRA762_ACD_ES1_0: case DRA762_ES1_0: pads = dra76x_core_padconf_array; npads = ARRAY_SIZE(dra76x_core_padconf_array); iodelay = dra76x_es1_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array); break; default: case DRA752_ES2_0: case DRA762_ABZ_ES1_0: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); /* Setup port1 and port2 for rgmii with 'no-id' mode */ clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | RGMII1_ID_MODE_N_MASK); break; } /* Setup I/O isolation */ ret = __recalibrate_iodelay_start(); if (ret) goto err; /* Do the muxing here */ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); /* Now do the weird minor deltas that should be safe */ if (delta_npads) do_set_mux32((*ctrl)->control_padconf_core_base, delta_pads, delta_npads); if (is_dra76x()) /* Set mux for MCAN instead of DCAN1 */ clrsetbits_le32((*ctrl)->control_core_control_spare_rw, MCAN_SEL_ALT_MASK, MCAN_SEL); /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); err: /* Closeup.. remove isolation */ __recalibrate_iodelay_end(ret); }