static void lpc_init(device_t dev) { u8 byte; u32 dword; device_t sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* RPR 7.2 Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); /* RPR 7.3 Disable the timeout mechanism on LPC */ byte = pci_read_config8(dev, 0x48); byte &= ~(1 << 7); pci_write_config8(dev, 0x48, byte); /* RPR 7.5 Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); cmos_check_update_date(); }
static void lpc_init(device_t dev) { u8 byte; u32 dword; device_t sm_dev; /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); /* Disable the timeout mechanism on LPC */ byte = pci_read_config8(dev, 0x48); byte &= ~(1 << 7); pci_write_config8(dev, 0x48, byte); /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going on on LPC, it holds PCI grant, so no LPC slave cycle can interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. * 1 tells cmos_init to always initialize the CMOS. */ cmos_init(0); /* Initialize i8259 pic */ setup_i8259 (); /* Initialize i8254 timers */ setup_i8254 (); }
static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. * 1 tells cmos_init to always initialize the CMOS. */ cmos_init(0); setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */ printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); }
static void rtc_init(void) { int rtc_fail; const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); if (!ps) { printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); return; } rtc_fail = !!(ps->gen_pmcon1 & RPS); /* Ensure the date is set including century byte. */ cmos_check_update_date(); if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) init_vbnv_cmos(rtc_fail); else cmos_init(rtc_fail); }
static void pch_rtc_init(void) { u8 reg8; int rtc_failed; /*PMC Controller Device 0x1F, Func 02*/ device_t dev = PCH_DEV_PMC; reg8 = pci_read_config8(dev, GEN_PMCON_B); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_B, reg8); printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } /* Ensure the date is set including century byte. */ cmos_check_update_date(); if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) init_vbnv_cmos(rtc_failed); else cmos_init(rtc_failed); }