static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
{
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
/* Disable the I2C */
I2C_CONTROLLER_REG = 0; /* Disabled the I2C */
//enable SCL and SDA which share pin with GPIOB_PIN_EN(0x18)
//GPIOB[12]: SCL
//GPIOB[13]: SDA
(*(u32*)(CNS3XXX_MISC_BASE_VIRT+0x18)) |= ((1<<12)|(1<<13));
MISC_IOCDB_CTRL &= ~0x300;
MISC_IOCDB_CTRL |= 0x300; //21mA...
/* Check the Reg Dump when testing */
I2C_TIME_OUT_REG =
((((((cns3xxx_cpu_clock()*(1000000/8)) / (2 * CNS3xxx_I2C_CLK)) -
1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
I2C_TWI_OUT_DLY_REG |= 0x3;
/* Enable The Interrupt */
CNS3xxx_I2C_ENABLE_INTR();
/* Clear Interrupt Status (0x2 | 0x1) */
I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG);
/* Enable the I2C Controller */
CNS3xxx_I2C_ENABLE();
}
static int cns3xxx_ehci_init(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
int retval;
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*
* Set USB AHB INCR length to 16
*/
if (atomic_inc_return(&usb_pwr_ref) == 1) {
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
MISC_CHIP_CONFIG_REG);
}
ehci->caps = hcd->regs;
hcd->has_tt = 0;
retval = ehci_setup(hcd);
if (retval)
return retval;
ehci_port_power(ehci, 0);
return retval;
}
static void __init cns3xxx_init(void)
{
struct device_node *dn;
cns3xxx_l2x0_init();
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
if (of_device_is_available(dn)) {
u32 tmp;
tmp = __raw_readl(MISC_SATA_POWER_MODE);
tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
__raw_writel(tmp, MISC_SATA_POWER_MODE);
/* Enable SATA PHY */
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
if (of_device_is_available(dn)) {
u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */
gpioa_pins |= 0x1fff0004;
__raw_writel(gpioa_pins, gpioa);
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
}
pm_power_off = cns3xxx_power_off;
of_platform_populate(NULL, of_default_bus_match_table,
cns3xxx_auxdata, NULL);
}
static void show_board_version(void)
{
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_GPIO);
cns3xxx_pwr_power_up(0x1 << PM_CLK_GATE_REG_OFFSET_GPIO);
cns3xxx_pwr_soft_rst(0x1 << PM_CLK_GATE_REG_OFFSET_GPIO);
printk("Technologic Systems TS-4300\n");
}
static void __init cns3xxx_spi_initial(void)
{
u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018);
u32 gpiob_pins = __raw_readl(gpiob);
/* MMC/SD pins share with GPIOA */
gpiob_pins |= 0xf80;
__raw_writel(gpiob_pins, gpiob);
/* share pin config. */
//PM_PLL_HM_PD_CTRL_REG &= ~(0x1 << 5);
//HAL_MISC_ENABLE_SPI_PINS();
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */
(0x0 << 9) | /* SPI mode */
(0x0 << 10) | /* disable FIFO */
(0x1 << 11) | /* SPI master mode */
(0x0 << 12) | /* disable SPI loopback mode */
(0x1 << 13) | /* clock phase */
(0x1 << 14) | /* clock polarity */
(0x0 << 24) | /* disable - SPI data swap */
(0x1 << 29) | /* enable - 2IO Read mode */
(0x0 << 30) | /* disable - SPI high speed read for system boot up */
(0x0 << 31)); /* disable - SPI */
/* Set SPI bit rate PCLK/2 */
SPI_BIT_RATE_CONTROL_REG = 0x1;
/* Set SPI Tx channel 0 */
SPI_TRANSMIT_CONTROL_REG = 0x0;
/* Set Tx FIFO Threshold, Tx FIFO has 2 words */
SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4);
SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4);
/* Set Rx FIFO Threshold, Rx FIFO has 2 words */
SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4);
SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4);
/* Disable all interrupt */
SPI_INTERRUPT_ENABLE_REG = 0x0;
/* Clear spurious interrupt sources */
SPI_INTERRUPT_STATUS_REG = (0x0F << 4);
/* Enable SPI */
SPI_CONFIGURATION_REG |= (0x1 << 31);
return;
}
static void __init ts43xx_map_io(void)
{
cns3xxx_map_io();
#ifdef CONFIG_SERIAL_8250_CONSOLE
HAL_MISC_ENABLE_UART1_PINS();
cns3xxx_pwr_power_up(CNS3XXX_PWR_PLL(PLL_USB));
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(UART1));
early_serial_setup(&cns3xxx_serial_ports[0]);
#if (1 < CONFIG_SERIAL_8250_NR_UARTS)
HAL_MISC_ENABLE_UART1_PINS();
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(UART1));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(UART1));
early_serial_setup(&cns3xxx_serial_ports[1]);
#endif
#if (2 < CONFIG_SERIAL_8250_NR_UARTS)
HAL_MISC_ENABLE_UART2_PINS();
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(UART2));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(UART2));
early_serial_setup(&cns3xxx_serial_ports[2]);
#endif
#endif
}
static int csn3xxx_usb_power_on(struct platform_device *pdev)
{
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*
* Set USB AHB INCR length to 16
*/
if (atomic_inc_return(&usb_pwr_ref) == 1) {
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
MISC_CHIP_CONFIG_REG);
}
return 0;
}
static void __init ts43xx_ahci_init(void)
{
u32 tmp;
tmp = MISC_SATA_POWER_MODE;
//tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp &= ~(0x1 << 16); /* Force SATA PHY 0 into SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
MISC_SATA_POWER_MODE = tmp;
/* Enable SATA PHY */
// ts43xx only uses port 1
//cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
static int __devinit
cns3xxx_ohci_start(struct usb_hcd *hcd)
{
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
int ret;
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*
* Set USB AHB INCR length to 16
*/
if (atomic_inc_return(&usb_pwr_ref) == 1) {
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
MISC_CHIP_CONFIG_REG);
}
ret = ohci_init(ohci);
if (ret < 0)
return ret;
ohci->num_ports = 1;
ret = ohci_run(ohci);
if (ret < 0) {
err("can't start %s", hcd->self.bus_name);
ohci_stop(hcd);
return ret;
}
return 0;
}
static int __devinit
cns3xxx_ohci_start(struct usb_hcd *hcd)
{
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
int ret;
/*
*/
if (atomic_inc_return(&usb_pwr_ref) == 1) {
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
MISC_CHIP_CONFIG_REG);
}
ret = ohci_init(ohci);
if (ret < 0)
return ret;
ohci->num_ports = 1;
ret = ohci_run(ohci);
if (ret < 0) {
err("can't start %s", hcd->self.bus_name);
ohci_stop(hcd);
return ret;
}
return 0;
}
static void __init cns3xxx_init(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
cns3xxx_l2x0_init();
#endif
#ifdef CONFIG_CACHE_L2CC
l2cc_init((void __iomem *) CNS3XXX_L2C_BASE_VIRT);
#endif
#ifdef CONFIG_CNS3XXX_DMAC
dmac_init();
#endif
#ifdef CONFIG_CNS3XXX_RAID
cns_rdma_init();
#endif
show_board_version();
{
volatile unsigned long *pciecfg0;
pciecfg0 = (volatile unsigned long *)CNS3XXX_PCIE0_CFG0_BASE_VIRT;
pciecfg0[1] |= 7;
printk("usec at kernel start: 0x%08lX\n", *(volatile unsigned long *)(CNS3XXX_PCIE0_MEM_BASE_VIRT+0x14));
}
ts43xx_ahci_init();
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
int ret;
cns3xxx_pwr_power_up(CNS3XXX_PWR_PLL(PLL_LCD));
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(LCDC));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(LCDC));
ret = amba_device_register(d, &iomem_resource);
if(ret)
printk("%s=>%d: %d\n", __FUNCTION__, __LINE__, ret);
}
platform_add_devices(cns3xxx_devs, ARRAY_SIZE(cns3xxx_devs));
lm_device_register(&cns3xxx_usb_otg_device);
i2c_register_board_info(0, cns3xxx_i2c_devices, ARRAY_SIZE(cns3xxx_i2c_devices));
i2c_register_board_info(1, cns3xxx_i2c_gpio_devices, ARRAY_SIZE(cns3xxx_i2c_gpio_devices));
spi_register_board_info(cns3xxx_spi_devices, ARRAY_SIZE(cns3xxx_spi_devices));
cns3xxx_proc_dir = proc_mkdir("cns3xxx", NULL);
#ifdef CONFIG_DEBUG_FS
cns3xxx_debugfs_dir = debugfs_create_dir("cns3xxx", NULL);
#endif
#ifdef CONFIG_CACHE_L2CC
l2cc_proc_init();
#endif
pm_power_off = cns3xxx_power_off;
}
static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
{
int port = cnspci->port;
struct pci_sys_data sd = {
.private_data = cnspci,
};
struct pci_bus bus = {
.number = 0,
.ops = &cns3xxx_pcie_ops,
.sysdata = &sd,
};
u16 mem_base = cnspci->res_mem.start >> 16;
u16 mem_limit = cnspci->res_mem.end >> 16;
u16 io_base = cnspci->res_io.start >> 16;
u16 io_limit = cnspci->res_io.end >> 16;
u32 devfn = 0;
u8 tmp8;
u16 pos;
u16 dc;
pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit);
pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit);
if (!cnspci->linked)
return;
/* Set Device Max_Read_Request_Size to 128 byte */
bus.number = 1; /* directly connected PCIe device */
devfn = PCI_DEVFN(0, 0);
pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
if (dc & PCI_EXP_DEVCTL_READRQ) {
dc &= ~PCI_EXP_DEVCTL_READRQ;
pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
if (dc & PCI_EXP_DEVCTL_READRQ)
pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
else
pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
}
/* Disable PCIe0 Interrupt Mask INTA to INTD */
__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
}
static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
{
if (fsr & (1 << 10))
regs->ARM_pc += 4;
return 0;
}
void __init cns3xxx_pcie_init_late(void)
{
int i;
void *private_data;
struct hw_pci hw_pci = {
.nr_controllers = 1,
.ops = &cns3xxx_pcie_ops,
.setup = cns3xxx_pci_setup,
.map_irq = cns3xxx_pcie_map_irq,
.private_data = &private_data,
};
pcibios_min_io = 0;
pcibios_min_mem = 0;
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
"imprecise external abort");
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
private_data = &cns3xxx_pcie[i];
pci_common_init(&hw_pci);
}
pci_assign_unassigned_resources();
}