static void __init realview_eb_init(void) { int i; if (core_tile_eb11mp() || core_tile_a9mp()) { realview_eb11mp_fixup(); #ifdef CONFIG_CACHE_L2X0 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled * Bits: .... ...0 0111 1001 0000 .... .... .... */ l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); #endif platform_device_register(&pmu_device); } realview_flash_register(&realview_eb_flash_resource, 1); platform_device_register(&realview_i2c_device); platform_device_register(&char_lcd_device); eth_device_register(); realview_usb_register(realview_eb_isp1761_resources); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); } #ifdef CONFIG_LEDS leds_event = realview_leds_event; #endif }
void __cpuinit platform_secondary_init(unsigned int cpu) { trace_hardirqs_off(); /* * the primary core may have used a "cross call" soft interrupt * to get this processor out of WFI in the BootMonitor - make * sure that we are no longer being sent this soft interrupt */ smp_cross_call_done(cpumask_of_cpu(cpu)); /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled * for us: do so */ if (machine_is_realview_eb() && core_tile_eb11mp()) gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); else if (machine_is_realview_pb11mp()) gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ pen_release = -1; smp_wmb(); /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); spin_unlock(&boot_lock); }
static void __init gic_init_irq(void) { if (core_tile_eb11mp() || core_tile_a9mp()) { unsigned int pldctrl; /* new irq mode */ writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); pldctrl |= 0x00800000; writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); /* core tile GIC, primary */ gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE), __io_address(REALVIEW_EB_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif } else { /* board GIC, primary */ gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE), __io_address(REALVIEW_EB_GIC_CPU_BASE)); } }
void __init smp_prepare_cpus(unsigned int max_cpus) { unsigned int ncores = get_core_count(); unsigned int cpu = smp_processor_id(); int i; /* sanity check */ if (ncores == 0) { printk(KERN_ERR "Realview: strange CM count of 0? Default to 1\n"); ncores = 1; } if (ncores > NR_CPUS) { printk(KERN_WARNING "Realview: no. of cores (%d) greater than configured " "maximum of %d - clipping\n", ncores, NR_CPUS); ncores = NR_CPUS; } smp_store_cpu_info(cpu); /* * are we trying to boot more cores than exist? */ if (max_cpus > ncores) max_cpus = ncores; #ifdef CONFIG_LOCAL_TIMERS /* * Enable the local timer for primary CPU. If the device is * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in * realview_timer_init */ if ((machine_is_realview_eb() && core_tile_eb11mp()) || machine_is_realview_pb11mp()) local_timer_setup(cpu); #endif /* * Initialise the present map, which describes the set of CPUs * actually populated at the present time. */ for (i = 0; i < max_cpus; i++) cpu_set(i, cpu_present_map); /* * Initialise the SCU if there are more than one CPU and let * them know where to start. Note that, on modern versions of * MILO, the "poke" doesn't actually do anything until each * individual core is sent a soft interrupt to get it out of * WFI */ if (max_cpus > 1) { scu_enable(); poke_milo(); } }
static void __init realview_eb_twd_init(void) { if (core_tile_eb11mp() || core_tile_a9mp()) { int err = twd_local_timer_register(&twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); } }
static void realview_eb_restart(char mode, const char *cmd) { void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK); __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); if (core_tile_eb11mp()) __raw_writel(0x0008, reset_ctrl); dsb(); }
static void realview_eb_reset(char mode) { void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK); /* * To reset, we hit the on-board reset register * in the system FPGA */ __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); if (core_tile_eb11mp()) __raw_writel(0x0008, reset_ctrl); }
/* * Setup the SCU */ static void scu_enable(void) { u32 scu_ctrl; void __iomem *scu_base; if (machine_is_realview_eb() && core_tile_eb11mp()) scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); else BUG(); scu_ctrl = __raw_readl(scu_base + SCU_CTRL); scu_ctrl |= 1; __raw_writel(scu_ctrl, scu_base + SCU_CTRL); }
static void __init realview_eb_timer_init(void) { unsigned int timer_irq; timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; if (core_tile_eb11mp() || core_tile_a9mp()) timer_irq = IRQ_EB11MP_TIMER0_1; else timer_irq = IRQ_EB_TIMER0_1; realview_timer_init(timer_irq); realview_eb_twd_init(); }
static unsigned int __init get_core_count(void) { unsigned int ncores; void __iomem *scu_base = 0; if (machine_is_realview_eb() && core_tile_eb11mp()) scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); if (scu_base) { ncores = __raw_readl(scu_base + SCU_CONFIG); ncores = (ncores & 0x03) + 1; } else ncores = 1; return ncores; }
static void __init realview_eb_timer_init(void) { unsigned int timer_irq; timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; if (core_tile_eb11mp() || core_tile_a9mp()) { #ifdef CONFIG_LOCAL_TIMERS twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE); #endif timer_irq = IRQ_EB11MP_TIMER0_1; } else timer_irq = IRQ_EB_TIMER0_1; realview_timer_init(timer_irq); }
static void __init realview_eb_map_io(void) { iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); if (core_tile_eb11mp() || core_tile_a9mp()) iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); }