/* * Setup the architecture */ static void __init stx_gp3_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("stx_gp3_setup_arch()", 0); #ifdef CONFIG_CPM2 cpm2_reset(); #endif #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8540-pci") fsl_add_bridge(np, 1); #endif }
/* * Setup the architecture */ static void __init ksi8560_setup_arch(void) { struct device_node *cpld; cpld = of_find_compatible_node(NULL, NULL, "emerson,KSI8560-cpld"); if (cpld) cpld_base = of_iomap(cpld, 0); else printk(KERN_ERR "Can't find CPLD in device tree\n"); if (ppc_md.progress) ppc_md.progress("ksi8560_setup_arch()", 0); #ifdef CONFIG_CPM2 cpm2_reset(); init_ioports(); #endif }
static void __init pq2fads_setup_arch(void) { struct device_node *np; __be32 __iomem *bcsr; if (ppc_md.progress) ppc_md.progress("pq2fads_setup_arch()", 0); cpm2_reset(); np = of_find_compatible_node(NULL, NULL, "fsl,pq2fads-bcsr"); if (!np) { printk(KERN_ERR "No fsl,pq2fads-bcsr in device tree\n"); return; } bcsr = of_iomap(np, 0); of_node_put(np); if (!bcsr) { printk(KERN_ERR "Cannot map BCSR registers\n"); return; } /* Enable the serial and ethernet ports */ clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); setbits32(&bcsr[1], BCSR1_FETH_RST); clrbits32(&bcsr[3], BCSR3_FETHIEN2); setbits32(&bcsr[3], BCSR3_FETH2_RST); iounmap(bcsr); init_ioports(); /* Enable external IRQs */ clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000); pq2_init_pci(); if (ppc_md.progress) ppc_md.progress("pq2fads_setup_arch(), finish", 0); }
static void __init mpc85xx_ads_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("mpc85xx_ads_setup_arch()", 0); #ifdef CONFIG_CPM2 cpm2_reset(); init_ioports(); #endif #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8540-pci") fsl_add_bridge(np, 1); ppc_md.pci_exclude_device = mpc85xx_exclude_device; #endif }
static void __init m8260_setup_arch(void) { /* Print out Vendor and Machine info. */ printk(KERN_INFO "%s %s port\n", CPUINFO_VENDOR, CPUINFO_MACHINE); /* Reset the Communication Processor Module. */ cpm2_reset(); #ifdef CONFIG_8260_PCI9 /* Initialise IDMA for PCI erratum workaround */ idma_pci9_init(); #endif #ifdef CONFIG_PCI_8260 m8260_find_bridges(); #endif #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; #endif m82xx_board_setup(); }
static void __init ep8248e_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("ep8248e_setup_arch()", 0); cpm2_reset(); /* When this is set, snooping CPM DMA from RAM causes * machine checks. See erratum SIU18. */ clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); ep8248e_bcsr_node = of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); if (!ep8248e_bcsr_node) { printk(KERN_ERR "No bcsr in device tree\n"); return; } ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0); if (!ep8248e_bcsr) { printk(KERN_ERR "Cannot map BCSR registers\n"); of_node_put(ep8248e_bcsr_node); ep8248e_bcsr_node = NULL; return; } setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE); setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER | BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER); init_ioports(); if (ppc_md.progress) ppc_md.progress("ep8248e_setup_arch(), finish", 0); }
/* ************************************************************************ * * Setup the architecture * */ static void __init tqm85xx_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; #ifdef CONFIG_MPC8560 cpm2_reset(); #endif /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("tqm85xx_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif #ifndef CONFIG_MPC8560 #if defined(CONFIG_SERIAL_8250) mpc85xx_early_serial_map(); #endif #ifdef CONFIG_SERIAL_TEXT_DEBUG /* Invalidate the entry we stole earlier the serial ports * should be properly mapped */ invalidate_tlbcam_entry(num_tlbcam_entries - 1); #endif #endif /* CONFIG_MPC8560 */ /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[0] = MPC85xx_IRQ_EXT8; mdata->irq[1] = MPC85xx_IRQ_EXT8; mdata->irq[2] = -1; mdata->irq[3] = MPC85xx_IRQ_EXT8; mdata->irq[31] = -1; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 2; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 1; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } #ifdef CONFIG_MPC8540 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); if (pdata) { pdata->board_flags = 0; pdata->bus_id = 0; pdata->phy_id = 3; memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); } #endif #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
/* * Setup the architecture */ static void __init gp3_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; cpm2_reset(); /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("gp3_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[2] = MPC85xx_IRQ_EXT5; mdata->irq[4] = MPC85xx_IRQ_EXT5; mdata->irq[31] = -1; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ pdata->bus_id = 0; pdata->phy_id = 2; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ pdata->bus_id = 0; pdata->phy_id = 4; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base); }
static void __init mpc8560ads_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; struct fs_platform_info *fpi; cpm2_reset(); /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("mpc8560ads_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[0] = MPC85xx_IRQ_EXT5; mdata->irq[1] = MPC85xx_IRQ_EXT5; mdata->irq[2] = PHY_POLL; mdata->irq[3] = MPC85xx_IRQ_EXT5; mdata->irq[31] = PHY_POLL; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 0; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 1; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } init_fcc_ioports(); ppc_sys_device_remove(MPC85xx_CPM_FCC1); fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2); if (fpi) { memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->bus_id = "0:02"; fpi->phy_addr = 2; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1]; } fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3); if (fpi) { memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->macaddr[5] += 1; fpi->bus_id = "0:03"; fpi->phy_addr = 3; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2]; } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
static void __init mpc8560ads_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; struct fs_platform_info *fpi; struct fs_mii_bb_platform_info *bb_pdata; cpm2_reset(); /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("mpc8560ads_setup_arch()", 0); #if !defined(CONFIG_BDI_SWITCH) /* * The Abatron BDI JTAG debugger does not tolerate others * mucking with the debug registers. */ mtspr(SPRN_DBCR0, (DBCR0_IDM)); mtspr(SPRN_DBSR, 0xffffffff); #endif /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[0] = MPC85xx_IRQ_EXT5; mdata->irq[1] = MPC85xx_IRQ_EXT5; mdata->irq[2] = -1; mdata->irq[3] = -1; mdata->irq[31] = -1; bb_pdata = (struct fs_mii_bb_platform_info *) ppc_sys_get_pdata (MPC85xx_MDIO_BB); bb_pdata->irq[0] = -1; bb_pdata->irq[1] = -1; bb_pdata->irq[2] = MPC85xx_IRQ_EXT7; bb_pdata->irq[3] = MPC85xx_IRQ_EXT7; bb_pdata->irq[4] = -1; bb_pdata->irq[31] = -1; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR | FSL_GIANFAR_BRD_PHY_ANEG; pdata->bus_id = 0; pdata->phy_id = 0; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR | FSL_GIANFAR_BRD_PHY_ANEG; pdata->bus_id = 0; pdata->phy_id = 1; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } init_fcc_ioports(); ppc_sys_device_remove(MPC85xx_CPM_FCC1); ppc_sys_device_remove(MPC85xx_CPM_SCC1); ppc_sys_device_remove(MPC85xx_CPM_SCC2); ppc_sys_device_remove(MPC85xx_CPM_SCC3); ppc_sys_device_remove(MPC85xx_CPM_SCC4); fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2); if (fpi) { fpi->board_flags = FS_ENET_BRD_PHY_ANEG; memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->bus_id = "0:02"; fpi->phy_addr = 2; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1]; } fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3); if (fpi) { fpi->board_flags = FS_ENET_BRD_PHY_ANEG; memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->macaddr[5] += 1; fpi->bus_id = "0:03"; fpi->phy_addr = 3; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2]; } #ifdef CONFIG_MTD mpc85xx_ads_mtd_setup(); #endif #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }