gpa_t DECAF_get_phys_addr_with_pgd(CPUState* env, gpa_t pgd, gva_t addr)
{
if (env == NULL)
{
#ifdef DECAF_NO_FAIL_SAFE
return (INV_ADDR);
#else
env = cpu_single_env ? cpu_single_env : first_cpu;
#endif
}
gpa_t old = env->cp15.c2_base0;
gpa_t old1 = env->cp15.c2_base1;
gpa_t phys_addr;
env->cp15.c2_base0 = pgd;
env->cp15.c2_base1 = pgd;
phys_addr = cpu_get_phys_page_debug(env, addr & TARGET_PAGE_MASK);
env->cp15.c2_base0 = old;
env->cp15.c2_base1 = old1;
return (phys_addr | (addr & (~TARGET_PAGE_MASK)));
}
hwaddr safe_get_phys_page_debug(CPUOldState *env, target_ulong addr)
{
#ifdef TARGET_I386
if (kvm_enabled()) {
kvm_get_sregs(env);
}
#endif
return cpu_get_phys_page_debug(env, addr);
}
static hwaddr yagl_pa(target_ulong va)
{
hwaddr ret =
cpu_get_phys_page_debug(current_cpu, va);
if (ret == -1) {
return 0;
} else {
return ret;
}
}
hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
{
hwaddr phys_addr;
target_ulong page;
page = vaddr & TARGET_PAGE_MASK;
phys_addr = cpu_get_phys_page_debug(cs, page);
phys_addr += (vaddr & ~TARGET_PAGE_MASK);
return phys_addr;
}
hwaddr safe_get_phys_page_debug(CPUState *cpu, target_ulong addr)
{
CPUArchState *env = cpu->env_ptr;
#ifdef TARGET_I386
if (kvm_enabled()) {
kvm_get_sregs(cpu);
}
#endif
extern int matchMeInPidTid(CPUArchState *);
extern int getMePCVal(CPUArchState *);
extern int getMeContextId(CPUArchState *);
hwaddr hwa = cpu_get_phys_page_debug(env, addr);
if(matchMeInPidTid(env))
{
printf("%d %s %x=%x\n", getMeContextId(env), __FUNCTION__, getMePCVal(env), hwa);
}
return hwa;
}
gpa_t DECAF_get_phys_addr_with_pgd(CPUState* env, gpa_t pgd, gva_t addr)
{
if (env == NULL)
{
#ifdef DECAF_NO_FAIL_SAFE
return (INV_ADDR);
#else
env = cpu_single_env ? cpu_single_env : first_cpu;
#endif
}
target_ulong saved_cr3 = env->cr[3];
uint32_t phys_addr;
env->cr[3] = pgd;
phys_addr = cpu_get_phys_page_debug(env, addr & TARGET_PAGE_MASK);
env->cr[3] = saved_cr3;
return (phys_addr | (addr & (~TARGET_PAGE_MASK)));
}
void do_get_physic_address(struct Monitor *mon, const struct QDict *qdict)
{
uint64_t target_cr3 = qdict_get_int(qdict, "cr3");
uint64_t target_addr = qdict_get_int(qdict, "addr");
X86CPU *cpu = X86_CPU(ENV_GET_CPU((CPUArchState*)mba_mon_get_cpu()));
hwaddr page = target_addr & TARGET_PAGE_MASK;
//XXX([email protected]):Only one phase copied. Should be fully copied to resist changes.
X86CPU copied_cpu;
memcpy(&copied_cpu, cpu, sizeof(copied_cpu));
copied_cpu.env.cr[3] = target_cr3;
hwaddr phys_page = cpu_get_phys_page_debug((CPUState*)&copied_cpu, page);
if (phys_page == -1) {
monitor_printf(mon, "Cannot find physic page\n");
return;
}
hwaddr phys_addr = phys_page + (target_addr & ~TARGET_PAGE_MASK);
monitor_printf(mon, "physic address = %p\n", (void*)phys_addr);
}
void HELPER(dinero_access)(uint32_t addr,uint32_t rw, uint32_t size)
{
if(VPMU_enabled)
{
/* we first calculate IRQ into account
int mode = env->uncached_cpsr & CPSR_M;
if(mode == ARM_CPU_MODE_IRQ)
return;
*/
#if 0
char *state = &(GlobalVPMU.state);
char *timer_interrupt_exception = &(GlobalVPMU.timer_interrupt_exception);
/* In timer interrupt state */
if(unlikely(*state == 1 && *timer_interrupt_exception == 0)) {
return;
}
#endif
if(vpmu_simulator_status(&GlobalVPMU, VPMU_DCACHE_SIM)) {
if(rw == 0xff)/* PLD */
{
//cache_ref(env->regs[rd]+shift, D4XREAD , 32);
addr = env->regs[(addr>>16)&0xf] + (addr&0xfff);
rw = D4XREAD;
}
//evo0209
if (GlobalVPMU.cpu_model == 1)
{
//uint32_t pa = cpu_get_phys_page_debug(env, addr);
//uint32_t pt = pa & 0xFFFFE000; //cortex-a9 L1 cache has 256-entry, blocksize 32bytes, mask 13bits
//addr = (addr & 0x00001FFF) | pt;
addr = cpu_get_phys_page_debug(env, addr);
}
//evo0209 temp test
if (GlobalVPMU.iomem_test == 1)
{
//printf("helper I/O addr: %x", addr);
GlobalVPMU.iomem_test = 0;
GlobalVPMU.iomem_qemu++;
}
else
cache_ref(addr, rw, size);
//chiaheng
#if 0 /* Considering the performance impact of I/O memory accesses. */
if(cpu_get_phys_page_debug(env, addr) >= SYSTEM_RAM_START &&
cpu_get_phys_page_debug(env, addr) < SYSTEM_RAM_END){
/* The cache memory simulation. */
cache_ref(addr, rw, size);
}
else {
/* Accounting for I/O memory accesses. */
GlobalVPMU.iomem_count++;
#if 0 /* Debuggin. */
if (cpu_get_phys_page_debug(env, addr) >= VPMU_BASE_ADDR
&& cpu_get_phys_page_debug(env, addr) < (VPMU_BASE_ADDR+VPMU_IOMEM_SIZE)) {
printf("%s: Address (virtual, physical) = (%x, %x).\n",
__FUNCTION__, addr, cpu_get_phys_page_debug(env, addr));
//fflush(stdout);
}
#endif
}
#endif
}
}
static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
XtensaCPU *cpu = opaque;
return cpu_get_phys_page_debug(CPU(cpu), addr);
}
static uint64_t translate_phys_addr(void *env, uint64_t addr)
{
return cpu_get_phys_page_debug(env, addr);
}
