static ssize_t dvfs_debug_store(struct sys_device *dev, struct sysdev_attribute *attr, const char *buf, size_t size) { u32 curr_ahb, curr_cpu, rate = 0; curr_ahb = clk_get_rate(ahb_clk); curr_cpu = clk_get_rate(cpu_clk); if (strstr(buf, "inc") != NULL) { rate = 4 * curr_ahb; pr_debug("inc to %d\n", rate); } if (strstr(buf, "dec") != NULL) { rate = ((curr_cpu / curr_ahb) - 1) * curr_ahb; if ((cpu_is_mx31_rev(CHIP_REV_2_0) < 0) && ((curr_cpu / curr_ahb) == 4)) rate = ((curr_cpu / curr_ahb) - 2) * curr_ahb; pr_debug("dec to %d\n", rate); } clk_set_rate(cpu_clk, rate); return size; }
static irqreturn_t dvfs_irq(int irq, void *dev_id) { u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); u32 fsvai = (pmcr0 & MXC_CCM_PMCR0_FSVAI_MASK) >> MXC_CCM_PMCR0_FSVAI_OFFSET; u32 dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >> MXC_CCM_PMCR0_DVSUP_OFFSET; u32 curr_ahb, curr_cpu, rate; /* Should not be here if FSVAIM is set */ BUG_ON(pmcr0 & MXC_CCM_PMCR0_FSVAIM); if (fsvai == FSVAI_FREQ_NOCHANGE) { /* Do nothing. Freq change is not required */ printk(KERN_WARNING "fsvai should not be 0\n"); return IRQ_HANDLED; } if (!(pmcr0 & MXC_CCM_PMCR0_UPDTEN)) { /* Do nothing. DVFS didn't finish previous flow update */ return IRQ_HANDLED; } if (((dvsup == DVSUP_LOW) && (fsvai == FSVAI_FREQ_DECREASE)) || ((dvsup == DVSUP_TURBO) && ((fsvai == FSVAI_FREQ_INCREASE) || (fsvai == FSVAI_FREQ_EMERG)))) { /* Interrupt should be disabled in these cases according to * the spec since DVFS is already at lowest (highest) state */ printk(KERN_WARNING "Something is wrong?\n"); return IRQ_HANDLED; } curr_ahb = clk_get_rate(ahb_clk); if (fsvai == FSVAI_FREQ_DECREASE) { curr_cpu = clk_get_rate(cpu_clk); rate = ((curr_cpu / curr_ahb) - 1) * curr_ahb; if ((cpu_is_mx31_rev(CHIP_REV_2_0) < 0) && ((curr_cpu / curr_ahb) == 4)) { rate = ((curr_cpu / curr_ahb) - 2) * curr_ahb; } dvfs_nr_dn[dvsup]++; } else { rate = 4 * curr_ahb; dvfs_nr_up[dvsup]++; } clk_set_rate(cpu_clk, rate); return IRQ_HANDLED; }
void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr) { if (cpu_is_mx31_rev(CHIP_REV_1_0) == 1) { sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR; sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR; sdma_script_addr->mxc_sdma_dptc_dvfs_addr = dptc_dvfs_ADDR; sdma_script_addr->mxc_sdma_firi_2_mcu_addr = firi_2_mcu_ADDR; sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = mshc_2_mcu_ADDR; sdma_script_addr->mxc_sdma_per_2_app_addr = -1; sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; sdma_script_addr->mxc_sdma_per_2_shp_addr = -1; sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; sdma_script_addr->mxc_sdma_mcu_2_firi_addr = mcu_2_firi_ADDR; sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = mcu_2_mshc_ADDR; sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; sdma_script_addr->mxc_sdma_uartsh_2_per_addr = -1; sdma_script_addr->mxc_sdma_shp_2_per_addr = -1; sdma_script_addr->mxc_sdma_uart_2_per_addr = -1; sdma_script_addr->mxc_sdma_app_2_per_addr = -1; } else { sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_2; sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = ap_2_ap_fixed_addr_ADDR_2; sdma_script_addr->mxc_sdma_ap_2_bp_addr = ap_2_bp_ADDR_2; sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = ap_2_ap_fixed_addr_ADDR_2; sdma_script_addr->mxc_sdma_bp_2_ap_addr = bp_2_ap_ADDR_2; sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_2; sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_2; sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code_2; sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_2; sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR_2; sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; sdma_script_addr->mxc_sdma_firi_2_mcu_addr = firi_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = mshc_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR_2; sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR_2; sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR_2; sdma_script_addr->mxc_sdma_mcu_2_firi_addr = mcu_2_firi_ADDR_2; sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = mcu_2_mshc_ADDR_2; sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR_2; sdma_script_addr->mxc_sdma_uartsh_2_per_addr = -1; sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR_2; sdma_script_addr->mxc_sdma_uart_2_per_addr = -1; sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR_2; } }