Esempio n. 1
0
static void usbh2_set_serial_xcvr(void)
{
	pr_debug("%s: \n", __func__);

	/* Stop then Reset */
	UH2_USBCMD &= ~UCMD_RUN_STOP;
	while (UH2_USBCMD & UCMD_RUN_STOP)
		;

	UH2_USBCMD |= UCMD_RESET;
	while (UH2_USBCMD & UCMD_RESET)
		;

	USBCTRL &= ~(UCTRL_H2SIC_MASK);	/* Disable bypass mode */
	USBCTRL &= ~(UCTRL_H2PM);	/* Power Mask */
	USBCTRL &= ~UCTRL_H2OCPOL;	/* OverCurrent Polarity is Low Active */
	USBCTRL &= ~UCTRL_H2WIE;	/* Wakeup intr disable */
	USBCTRL |= UCTRL_IP_PUE_DOWN |	/* ipp_pue_pulldwn_dpdm */
	    UCTRL_USBTE |	/* USBT is enabled */
	    UCTRL_H2DT;		/* Disable H2 TLL */

	if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) {
		/* Disable Host2 bus Lock for i.MX35 1.0 */
		USBCTRL |= UCTRL_H2LOCKD;
		/* USBOTG_PWR low active */
		USBCTRL &= ~UCTRL_PP;
		/* OverCurrent Polarity is Low Active */
		USBCTRL &= ~UCTRL_OCPOL;
	} else if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) {
		/* i.MX35 2.0 OTG and Host2 have seperate OC/PWR polarity */
		USBCTRL &= ~UCTRL_H2PP;
		USBCTRL &= ~UCTRL_H2OCPOL;
	} else if (cpu_is_mx25()) {
		/*
		 * USBH2_PWR and USBH2_OC are active high.
		 * Must force xcvr clock to "internal" so that
		 * we can write to PTS field after it's been
		 * cleared by ehci_turn_off_all_ports().
		 */
		USBCTRL |= UCTRL_H2PP | UCTRL_H2OCPOL | UCTRL_XCSH2;
		/* Disable Host2 bus Lock */
		USBCTRL |= UCTRL_H2LOCKD;
	}

	USBCTRL &= ~(UCTRL_PP);
	UH2_PORTSC1 = (UH2_PORTSC1 & (~PORTSC_PTS_MASK)) | PORTSC_PTS_SERIAL;

	if (UH2_HCSPARAMS & HCSPARAMS_PPC)
		UH2_PORTSC1 |= PORTSC_PORT_POWER;

	/* Reset controller before set host mode */
	UH2_USBCMD |= UCMD_RESET;
	while (UH2_USBCMD & UCMD_RESET)
		;

	msleep(100);
}
Esempio n. 2
0
/*!
 * Currently not called. If the Luigi Audio design decides to use
 * ASRC, then a call to this will be added in the __init fn
 */
static inline void mxc_init_asrc(void)
{
	if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1)
		mxc_asrc_data.channel_bits = 3;
	else
		mxc_asrc_data.channel_bits = 4;

	mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
	clk_put(mxc_asrc_data.asrc_core_clk);
	mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_audio_clk");
	clk_set_rate(mxc_asrc_data.asrc_audio_clk, 768000);
	clk_put(mxc_asrc_data.asrc_audio_clk);
	platform_device_register(&mxc_asrc_device);
}
Esempio n. 3
0
struct cpu_wp *get_cpu_wp(int *wp)
{
	if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) {
		*wp = 9;
		return cpu_wp_con;
	} else {
		if (__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON) {
			*wp = 9;
			return cpu_wp_con;
		} else {
			*wp = 6;
			return cpu_wp_auto;
		}
	}
}
Esempio n. 4
0
static int __init dvfs_init(void)
{
	int err = 0;
	u8 index;
	unsigned long curr_cpu;
	static struct regulator *sw2_dvs_reg, *sw1_wifi_reg, *sw4_reg;
	static struct regulator *viohi_reg, *vdig_reg, *swbst_reg, *vpll_reg, *vusb2_reg;	
	static struct regulator *sw2_stdby_reg, *sw3_normal_reg, *sw1_stby_reg;
	int finid = get_pmic_revision();
	unsigned int reg = 0;

	cpu_clk = clk_get(NULL, "cpu_clk");
	curr_cpu = clk_get_rate(cpu_clk);
	sw3_reg = regulator_get(NULL, "SW2");
	dvfs_is_active = 0;

	printk(KERN_INFO "Initializing MX35 DVFS on MC13892 Finid: %d\n", finid);

	/*
	 * WIFI SW1 - Turn off by default
	 */
	sw1_wifi_reg = regulator_get(NULL, "SW1");
	sw1_stby_reg = regulator_get(NULL, "SW1_STBY");
	regulator_enable(sw1_wifi_reg);
	regulator_set_voltage(sw1_wifi_reg, 0, 0);
	pmic_write_reg(28, 0, 0xf << 0);  /* Set to off in Normal mode */
	pmic_write_reg(24, 0, 0x1f << 0); /* Set 0V in Normal mode */
	regulator_set_voltage(sw1_stby_reg, 1200000, 1200000);
	if (finid == 2)
		pmic_write_reg(28, (0x0 << 0), (0xf << 0));
	mdelay(10);

	/*
	 * CPU SW2
	 */
	pmic_write_reg(25, (1 << 23), (1 << 23));
	sw2_dvs_reg = regulator_get(NULL, "SW2_DVS");
	sw2_stdby_reg = regulator_get(NULL, "SW2_STBY");
	regulator_set_voltage(sw2_dvs_reg, 1400000, 1400000);
	regulator_set_voltage(sw3_reg, 1400000, 1400000);
	regulator_set_voltage(sw2_stdby_reg, 1100000, 1100000);

	/*
	 * Turn off SW3
	 */
	sw3_normal_reg = regulator_get(NULL, "SW3");
	regulator_set_voltage(sw3_normal_reg, 0, 0);
	pmic_write_reg(29, 0, 0xf << 0); /* Set to off in Normal mode */
	pmic_write_reg(26, 0, 0x1f << 0); /* Set 0V in Normal mode */
	if (finid == 2)
		pmic_write_reg(28, (0x8 << 10), (0xf << 10));
	mdelay(20);

	/*
	 * Set SW4 to 1.8V by default
	 */
	if (finid == 2)
		pmic_write_reg(29, (0x8 << 8), (0xf << 8));
	sw4_reg = regulator_get(NULL, "SW4");
	regulator_set_voltage(sw4_reg, 1800000, 1800000);

	/* Set the SW4 Standby to 1.8V */
	pmic_write_reg(27, (0x1C << 10), (0x1f << 10));

	/*
	 * STANDBY and STANDBYSEC are both active low 
	 */
	pmic_write_reg(REG_POWER_CTL2, (0 << STANDBYINV), (1 << STANDBYINV));
	pmic_write_reg(REG_POWER_CTL2, (0 << STANDBYSECINV), (1 << STANDBYSECINV));

	/* Enable WDIRESET on the PMIC */
	pmic_write_reg(REG_POWER_CTL2, (1 << WDIRESET), (1 << WDIRESET));

	/* Turn on GPO2STBY to disable the regulator in Atlas standby mode */
	pmic_write_reg(REG_POWER_MISC, (GPO2STBY_ENABLE << GPO2STBY_LSH),
			(GPO2STBY_MASK << GPO2STBY_LSH));

	/*
	 * VIOHI
	 */
	viohi_reg = regulator_get(NULL, "VIOHI");
	regulator_enable(viohi_reg);

	/*
	 * VDIG
	 */
	vdig_reg = regulator_get(NULL, "VDIG");
	regulator_enable(vdig_reg);
	regulator_disable(vdig_reg);	

	/*
	 * VUSB2
	 */
	vusb2_reg = regulator_get(NULL, "VUSB2");
	regulator_enable(vusb2_reg);
	regulator_disable(vusb2_reg);

	/*
	 * SWBST - off
	 */
	swbst_reg = regulator_get(NULL, "SWBST");
	regulator_enable(swbst_reg);
	regulator_disable(swbst_reg);

	/* Turn off SWBST */
	pmic_write_reg(REG_SW_5, (0 << 20), (1 << 20));

	/*
	 * VPLL - Controlled by Standby
	 */
	vpll_reg = regulator_get(NULL, "VPLL");
	/* VPLL controlled by standby */
	pmic_write_reg(32, (1 << 16), (1 << 16));

	/*
	 * VSD - Controlled by Standby
	 */
	pmic_write_reg(33, (1 << 18), (1 << 18));
	pmic_write_reg(33, (1 << 19), (1 << 19));
	pmic_write_reg(32, (1 << 13), (1 << 13));

	/*
	 * Power button debounce time
	 */

	pmic_read_reg(REG_POWER_CTL2, &reg, 0xffffffff);
	printk(KERN_INFO "Power Button Debounce Settings: 0x%x\n", reg);

	/* Configure debounce time for power button 1 */
	pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 4), (PMIC_BUTTON_DEBOUNCE_MASK << 4));
	
	/* Configure debounce time for power button 2 */
	pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 6), (PMIC_BUTTON_DEBOUNCE_MASK << 6));

	/* Configure debounce time for power button 3 */
	pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 8), (PMIC_BUTTON_DEBOUNCE_MASK << 8));

	/*
	 * Set the USEROFF Mode for the Switchers
	 */
	pmic_write_reg(REG_SW_4, (SW1_MHMODE_VALUE << SW1_MHMODE_LSH),
			(SW1_MHMODE_MASK << SW1_MHMODE_LSH));

	pmic_write_reg(REG_SW_4, (SW2_MHMODE_VALUE << SW2_MHMODE_LSH),
			(SW2_MHMODE_MASK << SW2_MHMODE_LSH));

	pmic_write_reg(REG_SW_5, (SW3_MHMODE_VALUE << SW3_MHMODE_LSH),
			(SW3_MHMODE_MASK << SW3_MHMODE_LSH));

	pmic_write_reg(REG_SW_5, (SW4_MHMODE_VALUE << SW4_MHMODE_LSH),
			(SW4_MHMODE_MASK << SW4_MHMODE_LSH));

	/* for auto path, only 3 working points are supported */
	if (!(__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON)) {
		if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) {
			dvfs_wp_num = 3;
			dvfs_wp_tbl[2].dvsup = DVFS_DVSUP(DVSUP_TURBO);
		}
	}

	printk(KERN_INFO "MX35 Luigi working points: %d\n", dvfs_wp_num);

	/*Set voltage */
	for (index = 0; index < dvfs_wp_num; index++) {
		if (dvfs_wp_tbl[index].cpu_rate == curr_cpu) {
			regulator_set_voltage(sw3_reg,
					      dvfs_wp_tbl[index].core_voltage,
					      dvfs_wp_tbl[index].core_voltage);
			break;
		}
	}

	err = init_dvfs_controller();
	if (err) {
		printk(KERN_ERR "DVFS: Unable to initialize DVFS");
		return err;
	}

	INIT_DELAYED_WORK(&dvfs_work, dvfs_workqueue_handler);

	/* request the DVFS interrupt */
	err = request_irq(MXC_INT_DVFS, dvfs_irq, IRQF_DISABLED, "dvfs", NULL);
	if (err) {
		printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt");
		return err;
	}

	err = dvfs_sysdev_ctrl_init();
	if (err) {
		printk(KERN_ERR
		       "DVFS: Unable to register sysdev entry for dvfs");
		return err;
	}

	return err;
}
Esempio n. 5
0
static void otg_set_utmi_xcvr(void)
{
	u32 tmp;

	/* Stop then Reset */
	UOG_USBCMD &= ~UCMD_RUN_STOP;
	while (UOG_USBCMD & UCMD_RUN_STOP) ;

	UOG_USBCMD |= UCMD_RESET;
	while ((UOG_USBCMD) & (UCMD_RESET)) ;

	if (cpu_is_mx51()) {
		/* OTG Polarity of Overcurrent is Low active */
		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL;
		/* Enable OTG Overcurrent Event */
		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS;
	} else if (cpu_is_mx25()) {
		USBCTRL |= UCTRL_OCPOL;
		USBCTRL &= ~UCTRL_PP;
	} else {
		/* USBOTG_PWR low active */
		USBCTRL &= ~UCTRL_PP;
		/* OverCurrent Polarity is Low Active */
		USBCTRL &= ~UCTRL_OCPOL;

		if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0)
			/* OTG Lock Disable */
			USBCTRL |= UCTRL_OLOCKD;
	}

	USBCTRL &= ~UCTRL_OPM;	/* OTG Power Mask */
	USBCTRL |= UCTRL_OWIE;	/* OTG Wakeup Intr Enable */

	/* set UTMI xcvr */
	tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK;
	tmp |= PORTSC_PTS_UTMI;
	UOG_PORTSC1 = tmp;

	if (cpu_is_mx51()) {
		/* Set the PHY clock to 19.2MHz */
		USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK;
		USB_PHY_CTR_FUNC2 |= 0x01;
	}
	if (!cpu_is_mx25()) {
		/* Workaround an IC issue for 2.6.26 kernal:
		 * when turn off root hub port power, EHCI set
		 * PORTSC reserved bits to be 0, but PTW with 0
		 * means 8 bits tranceiver width, here change
		 * it back to be 16 bits and do PHY diable and
		 * then enable.
		 */
		UOG_PORTSC1 |= PORTSC_PTW;

		/* Enable UTMI interface in PHY control Reg */
		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE;
		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE;
	}

	if (UOG_HCSPARAMS & HCSPARAMS_PPC)
		UOG_PORTSC1 |= PORTSC_PORT_POWER;

	/* need to reset the controller here so that the ID pin
	 * is correctly detected.
	 */
	/* Stop then Reset */
	UOG_USBCMD &= ~UCMD_RUN_STOP;
	while (UOG_USBCMD & UCMD_RUN_STOP) ;

	UOG_USBCMD |= UCMD_RESET;
	while ((UOG_USBCMD) & (UCMD_RESET)) ;

	/* allow controller to reset, and leave time for
	 * the ULPI transceiver to reset too.
	 */
	msleep(100);

	/* Turn off the usbpll for mx25 UTMI tranceivers */
	/* DDD: can we do this UTMI xcvrs on all boards? */
	if (cpu_is_mx25())
		clk_disable(usb_clk);
}
Esempio n. 6
0
static void otg_set_utmi_xcvr(void)
{
	u32 tmp;

	/* Stop then Reset */
	UOG_USBCMD &= ~UCMD_RUN_STOP;
	while (UOG_USBCMD & UCMD_RUN_STOP)
		;

	UOG_USBCMD |= UCMD_RESET;
	while ((UOG_USBCMD) & (UCMD_RESET))
		;

	if (cpu_is_mx53())
		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;

	if (cpu_is_mx51()) {
		if (machine_is_mx51_3ds()) {
			/* OTG Polarity of Overcurrent is Low active */
			USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL;
			/* Enable OTG Overcurrent Event */
			USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS;
		} else {
			/* BBG is not using OC */
			USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
		}
	} else if (cpu_is_mx25()) {
		USBCTRL |= UCTRL_OCPOL;
		USBCTRL &= ~UCTRL_PP;
	} else if (cpu_is_mx50()) {
		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
	} else {
		/* USBOTG_PWR low active */
		USBCTRL &= ~UCTRL_PP;
		/* OverCurrent Polarity is Low Active */
		USBCTRL &= ~UCTRL_OCPOL;

		if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0)
			/* OTG Lock Disable */
			USBCTRL |= UCTRL_OLOCKD;
	}

	if (cpu_is_mx51())
		USBCTRL &= ~UCTRL_OPM;	/* OTG Power Mask */

	USBCTRL &= ~UCTRL_OWIE;	/* OTG Wakeup Intr Disable */

	/* set UTMI xcvr */
	tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK;
	tmp |= PORTSC_PTS_UTMI;
	UOG_PORTSC1 = tmp;

	if (cpu_is_mx51()) {
		/* Set the PHY clock to 19.2MHz */
		USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK;
		USB_PHY_CTR_FUNC2 |= 0x01;
	} else if (machine_is_mx37_3ds()) {
		/* Reference voltage for HS disconnect envelope detector */
		/* adjust the Squelch level */
		USB_PHY_CTR_FUNC2 &= ~(USB_UTMI_PHYCTRL2_HSDEVSEL_MASK <<
			USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT);
	}

	/* Workaround an IC issue for ehci driver:
	 * when turn off root hub port power, EHCI set
	 * PORTSC reserved bits to be 0, but PTW with 0
	 * means 8 bits tranceiver width, here change
	 * it back to be 16 bits and do PHY diable and
	 * then enable.
	 */
	UOG_PORTSC1 |= PORTSC_PTW;

	if (cpu_is_mx35() || cpu_is_mx25()) {
		/* Enable UTMI interface in PHY control Reg */
		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE;
		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE;
	}

	/* need to reset the controller here so that the ID pin
	 * is correctly detected.
	 */
	/* Stop then Reset */
	UOG_USBCMD &= ~UCMD_RUN_STOP;
	while (UOG_USBCMD & UCMD_RUN_STOP)
		;

	UOG_USBCMD |= UCMD_RESET;
	while ((UOG_USBCMD) & (UCMD_RESET))
		;

	/* allow controller to reset, and leave time for
	 * the ULPI transceiver to reset too.
	 */
	msleep(100);

	if (cpu_is_mx37()) {
		/* fix USB PHY Power Gating leakage issue for i.MX37 */
		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON;
		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN;
	}

	/* Turn off the usbpll for UTMI tranceivers */
	clk_disable(usb_clk);
}
Esempio n. 7
0
void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr)
{
	if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) {
		sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR;
		sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1;
		sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1;
		sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1;
		sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1;

		sdma_script_addr->mxc_sdma_firi_2_per_addr = -1;
		sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1;
		sdma_script_addr->mxc_sdma_per_2_firi_addr = -1;
		sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1;

		sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR;
		sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR;
		sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR;
		sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR;

		sdma_script_addr->mxc_sdma_per_2_per_addr = p_2_p_ADDR;

		sdma_script_addr->mxc_sdma_uartsh_2_per_addr =
		    uartsh_2_per_ADDR;
		sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr =
		    uartsh_2_mcu_ADDR;
		sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR;
		sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR;

		sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR;
		sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR;

		sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR;
		sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR;
		sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR;
		sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR;

		sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1;
		sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1;

		sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = spdif_2_mcu_ADDR;
		sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR;

		sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR;

		sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1;
		sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr =
		    ext_mem__ipu_ram_ADDR;
		sdma_script_addr->mxc_sdma_descrambler_addr = -1;

		sdma_script_addr->mxc_sdma_start_addr =
		    (unsigned short *)sdma_code;
		sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE;
		sdma_script_addr->mxc_sdma_ram_code_start_addr =
		    RAM_CODE_START_ADDR;
	} else {
		sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_V2;
		sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1;
		sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1;
		sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1;
		sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1;

		sdma_script_addr->mxc_sdma_firi_2_per_addr = -1;
		sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1;
		sdma_script_addr->mxc_sdma_per_2_firi_addr = -1;
		sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1;

		sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR_V2;
		sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_V2;
		sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR_V2;
		sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_V2;

		sdma_script_addr->mxc_sdma_per_2_per_addr = p_2_p_ADDR_V2;

		sdma_script_addr->mxc_sdma_uartsh_2_per_addr =
		    uartsh_2_per_ADDR_V2;
		sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr =
		    uartsh_2_mcu_ADDR_V2;
		sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR_V2;
		sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_V2;

		sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR_V2;
		sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR_V2;

		sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR_V2;
		sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_V2;
		sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR_V2;
		sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_V2;

		sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1;
		sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1;

		sdma_script_addr->mxc_sdma_spdif_2_mcu_addr =
		    spdif_2_mcu_ADDR_V2;
		sdma_script_addr->mxc_sdma_mcu_2_spdif_addr =
		    mcu_2_spdif_ADDR_V2;

		sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR_V2;

		sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1;
		sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr =
		    ext_mem__ipu_ram_ADDR_V2;
		sdma_script_addr->mxc_sdma_descrambler_addr = -1;

		sdma_script_addr->mxc_sdma_start_addr =
		    (unsigned short *)sdma_code_v2;
		sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE;
		sdma_script_addr->mxc_sdma_ram_code_start_addr =
		    RAM_CODE_START_ADDR_V2;
	}
}