static inline void * _get_pad_reg(iomux_pin_name_t pin)
{
u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
void __iomem *sw_pad_reg = _get_sw_pad();
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) {
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
(pin == MX51_PIN_NANDF_RB7))
; /* Do nothing */
else if (pad_reg == 0x4D0 - PAD_I_START_MX51)
pad_reg += 0x4C;
else if (pad_reg == 0x860 - PAD_I_START_MX51)
pad_reg += 0x9C;
else if (pad_reg >= 0x804 - PAD_I_START_MX51)
pad_reg += 0xB0;
else if (pad_reg >= 0x7FC - PAD_I_START_MX51)
pad_reg += 0xB4;
else if (pad_reg >= 0x4E4 - PAD_I_START_MX51)
pad_reg += 0xCC;
else
pad_reg += 8;
}
return sw_pad_reg + pad_reg;
}
/*!
* This function configures input path.
*
* @param input index of input select register as defined in \b #iomux_input_select_t
* @param config the binary value of elements defined in \b #iomux_input_config_t
* */
void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
{
void __iomem *reg;
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) {
if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT)
input -= 4;
else if (input == MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT)
input -= 3;
else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT)
input -= 2;
else if (input >= MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT)
input -= 5;
else if (input >= MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT)
input -= 3;
else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT)
input -= 2;
else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT)
input -= 1;
reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51_TO1;
} else if (cpu_is_mx51()) {
reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51;
} else
reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX53;
BUG_ON(input >= MUX_INPUT_NUM_MUX);
__raw_writel(config, reg);
}
static int headphone_det_status(void)
{
if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2)
return (gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14)) == 0);
return gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
}
static inline void * _get_mux_end(void)
{
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
return(IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F8 - 4));
else
return(IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F0 - 4));
}
/* All versions of the silicon before Rev. 3 have broken NEON implementations.
* Dependent on link order - so the assumption is that vfp_init is called before us
*/
static int __init mx51_neon_fixup(void)
{
if (cpu_is_mx51_rev(CHIP_REV_3_0) < 1 ) {
if (elf_hwcap & HWCAP_NEON) {
elf_hwcap &= ~HWCAP_NEON;
pr_info("Turning off NEON support, detected broken NEON implemention\n");
}
}
return 0;
}
/*!
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory map for
* the IO modules.
*/
void __init mxc_map_io(void)
{
u32 tzic_addr;
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
tzic_addr = 0x8FFFC000;
else
tzic_addr = 0xE0003000;
mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr);
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
static int __init usbh2_init(void)
{
pr_debug("%s: \n", __func__);
if (machine_is_mx51_3ds() ||
(machine_is_mx51_babbage() && (cpu_is_mx51_rev(CHIP_REV_2_0) >= 1)))
return 0;
host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources),
&usbh2_config);
return 0;
}
static void mxc_init_fb(void)
{
if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0)
lcd_data.reset = lcd_reset_to2;
(void)platform_device_register(&mxc_lcd_device);
(void)platform_device_register(&lcd_wvga_device);
(void)platform_device_register(&mxc_fb_device[0]);
(void)platform_device_register(&mxc_fb_device[1]);
(void)platform_device_register(&mxc_fb_device[2]);
}
static void mxc_init_ipu(void)
{
u32 reg_hsc_mcd = IO_ADDRESS(MIPI_HSC_BASE_ADDR);
u32 reg_hsc_mxt_conf = IO_ADDRESS(MIPI_HSC_BASE_ADDR + 0x800);
struct clk *clk;
uint32_t temp;
/* Select IPUv3 h/w version */
if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0)
mxc_ipu_data.rev = 2;
mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
clk = clk_get(NULL, "tve_clk");
clk_set_parent(mxc_ipu_data.di_clk[1], clk);
clk_put(clk);
/* Temporarily setup MIPI module to legacy mode */
clk = clk_get(NULL, "mipi_hsp_clk");
if (!IS_ERR(clk)) {
clk_enable(clk);
/* Temporarily setup MIPI module to legacy mode */
__raw_writel(0xF00, reg_hsc_mcd);
/* CSI mode reserved*/
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) {
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
}
clk_disable(clk);
clk_put(clk);
}
platform_device_register(&mxc_ipu_device);
}
static void __init mx51_babbage_timer_init(void)
{
struct clk *uart_clk;
/* Change the CPU voltages for TO2*/
if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) {
cpu_wp_auto[0].cpu_voltage = 1175000;
cpu_wp_auto[1].cpu_voltage = 1100000;
cpu_wp_auto[2].cpu_voltage = 1000000;
}
mx51_clocks_init(32768, 24000000, 22579200, 24576000);
uart_clk = clk_get(NULL, "uart_clk.0");
early_console_setup(UART1_BASE_ADDR, uart_clk);
}
static inline void * _get_mux_reg(iomux_pin_name_t pin)
{
u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) {
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
(pin == MX51_PIN_NANDF_RB7))
; /* Do nothing */
else if (mux_reg >= 0x2FC)
mux_reg += 8;
else if (mux_reg >= 0x130)
mux_reg += 0xC;
}
return IOMUXSW_MUX_CTL + mux_reg;
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1");
mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2");
mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
clk_put(mxc_spdif_data.spdif_core_clk);
/* SD card detect irqs */
mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6);
mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6);
mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
mxc_cpu_common_init();
mxc_register_gpios();
mx51_babbage_io_init();
mxc_register_device(&mxc_dma_device, NULL);
mxc_register_device(&mxc_wdt_device, NULL);
mxc_register_device(&mxcspi1_device, &mxcspi1_data);
mxc_register_device(&mxci2c_devices[0], &mxci2c_data);
mxc_register_device(&mxci2c_devices[1], &mxci2c_data);
mxc_register_device(&mxci2c_hs_device, &mxci2c_hs_data);
mxc_register_device(&mxc_rtc_device, &srtc_data);
mxc_register_device(&mxc_w1_master_device, &mxc_w1_data);
mxc_register_device(&mxc_ipu_device, &mxc_ipu_data);
mxc_register_device(&mxc_tve_device, &tve_data);
mxc_register_device(&mxcvpu_device, &mxc_vpu_data);
mxc_register_device(&gpu_device, NULL);
mxc_register_device(&mxcscc_device, NULL);
mxc_register_device(&mx51_lpmode_device, NULL);
mxc_register_device(&busfreq_device, NULL);
mxc_register_device(&sdram_autogating_device, NULL);
mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data);
mxc_register_device(&mxc_iim_device, NULL);
mxc_register_device(&mxc_pwm1_device, NULL);
mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data);
mxc_register_device(&mxc_keypad_device, &keypad_plat_data);
mxc_register_device(&mxcsdhc1_device, &mmc1_data);
mxc_register_device(&mxcsdhc2_device, &mmc2_data);
mxc_register_device(&mxc_ssi1_device, NULL);
mxc_register_device(&mxc_ssi2_device, NULL);
mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data);
mxc_register_device(&mxc_fec_device, NULL);
mxc_register_device(&mxc_v4l2_device, NULL);
mxc_register_device(&mxc_v4l2out_device, NULL);
mx51_babbage_init_mc13892();
if (board_is_rev(BOARD_REV_2))
/* BB2.5 */
spi_register_board_info(mxc_dataflash_device,
ARRAY_SIZE(mxc_dataflash_device));
else
/* BB2.0 */
spi_register_board_info(mxc_spi_nor_device,
ARRAY_SIZE(mxc_spi_nor_device));
i2c_register_board_info(0, mxc_i2c0_board_info,
ARRAY_SIZE(mxc_i2c0_board_info));
i2c_register_board_info(1, mxc_i2c1_board_info,
ARRAY_SIZE(mxc_i2c1_board_info));
if (cpu_is_mx51_rev(CHIP_REV_2_0) >= 1) {
vga_data.core_reg = NULL;
vga_data.io_reg = NULL;
vga_data.analog_reg = NULL;
}
i2c_register_board_info(3, mxc_i2c_hs_board_info,
ARRAY_SIZE(mxc_i2c_hs_board_info));
pm_power_off = mxc_power_off;
if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) {
sgtl5000_data.sysclk = 26000000;
}
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), "eim_a23");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), 0);
mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
mx5_usb_dr_init();
mx5_usbh1_init();
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
int err;
mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1");
mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2");
mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
clk_put(mxc_spdif_data.spdif_core_clk);
mxc_cpu_common_init();
mx51_3stack_io_init();
mxc_register_device(&mxc_dma_device, NULL);
mxc_register_device(&mxc_wdt_device, NULL);
mxc_register_device(&mxcspi1_device, &mxcspi1_data);
mxc_register_device(&mxci2c_devices[0], &mxci2c_data);
mxc_register_device(&mxci2c_devices[1], &mxci2c_data);
mxc_register_device(&mxci2c_hs_device, &mxci2c_hs_data);
mxc_register_device(&mxc_rtc_device, NULL);
mxc_register_device(&mxc_w1_master_device, &mxc_w1_data);
mxc_register_device(&mxc_ipu_device, &mxc_ipu_data);
mxc_register_device(&mxc_tve_device, &tve_data);
mxc_register_device(&mxcvpu_device, &mxc_vpu_data);
mxc_register_device(&gpu_device, NULL);
mxc_register_device(&mxcscc_device, NULL);
mxc_register_device(&mx51_lpmode_device, NULL);
mxc_register_device(&busfreq_device, &bus_freq_data);
mxc_register_device(&sdram_autogating_device, NULL);
mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data);
mxc_register_device(&mxc_iim_device, NULL);
mxc_register_device(&mxc_pwm1_device, NULL);
mxc_register_device(&mxc_pwm1_backlight_device,
&mxc_pwm_backlight_data);
mxc_register_device(&mxc_keypad_device, &keypad_plat_data);
mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
mxc_register_device(&mxcsdhc1_device, &mmc1_data);
mxc_register_device(&mxcsdhc2_device, &mmc2_data);
mxc_register_device(&mxc_sim_device, &sim_data);
mxc_register_device(&pata_fsl_device, &ata_data);
mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data);
mxc_expio_init();
if (debug_board_present)
mxc_register_device(&smsc_lan9217_device, &smsc911x_config);
if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0)
lcd_data.reset = lcd_reset_to2;
mxc_register_device(&mxc_lcd_device, &lcd_data);
mxc_register_device(&lcd_wvga_device, &lcd_wvga_data);
mxc_register_device(&mxc_fb_devices[0], &fb_data[0]);
mxc_register_device(&mxc_fb_devices[1], &fb_data[1]);
mxc_register_device(&mxc_fb_devices[2], NULL);
mxc_register_device(&mxcbl_device, NULL);
#if defined(CONFIG_MTD_NAND_IMX_NFC) || defined(CONFIG_MTD_NAND_IMX_NFC_MODULE)
mxc_register_device(&imx_nfc_device, &imx_nfc_platform_data);
#else
mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data);
#endif
mx51_3stack_init_mc13892();
i2c_register_board_info(1, mxc_i2c1_board_info,
ARRAY_SIZE(mxc_i2c1_board_info));
i2c_register_board_info(3, mxc_i2c_hs_board_info,
ARRAY_SIZE(mxc_i2c_hs_board_info));
mxc_init_wm8903();
mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
mxc_register_device(&mxc_bt_device, &mxc_bt_data);
mxc_register_device(&mxc_gps_device, &gps_data);
mxc_register_device(&mxc_v4l2_device, NULL);
mxc_register_device(&mxc_v4l2out_device, NULL);
mx5_usb_dr_init();
mx5_usbh1_init();
/* Setup Touchscreen interrupt */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), "gpio1_5");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5));
err = mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_GPIO);
if (err)
printk(KERN_ERR "Error: bt reset request gpio failed!\n");
else {
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D19), "eim_d19");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D19), 0);
}
}
static int handle_edid(int *pixclk)
{
#if 0
int err = 0;
int dvi = 0;
int fb0 = 0;
int fb1 = 1;
struct fb_var_screeninfo screeninfo;
struct i2c_adapter *adp;
memset(&screeninfo, 0, sizeof(screeninfo));
adp = i2c_get_adapter(1);
if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 1);
msleep(1);
}
err = read_edid(adp, &screeninfo, &dvi);
if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0)
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 0);
if (!err) {
printk(KERN_INFO " EDID read\n");
if (!dvi) {
enable_vga = 1;
fb0 = 1; /* fb0 will be VGA */
fb1 = 0; /* fb1 will be DVI or TV */
}
/* Handle TV modes */
/* This logic is fairly complex yet still doesn't handle all
possibilities. Once a customer knows the platform
configuration, this should be simplified to what is desired.
*/
if (screeninfo.xres == 1920 && screeninfo.yres != 1200) {
/* MX51 can't handle clock speeds for anything larger.*/
if (!enable_tv)
enable_tv = 1;
if (enable_vga || enable_wvga || enable_tv == 2)
enable_tv = 2;
fb_data[0].mode = &(video_modes[0]);
if (!enable_wvga)
fb_data[1].mode_str = "800x600M-16@60";
} else if (screeninfo.xres > 1280 && screeninfo.yres > 1024) {
if (!enable_wvga) {
fb_data[fb0].mode_str = "1280x1024M-16@60";
fb_data[fb1].mode_str = NULL;
} else {
/* WVGA is preset so the DVI can't be > this. */
fb_data[0].mode_str = "1024x768M-16@60";
}
} else if (screeninfo.xres > 0 && screeninfo.yres > 0) {
if (!enable_wvga) {
fb_data[fb0].mode =
kzalloc(sizeof(struct fb_videomode),
GFP_KERNEL);
fb_var_to_videomode(fb_data[fb0].mode,
&screeninfo);
fb_data[fb0].mode_str = NULL;
if (screeninfo.xres >= 1280 &&
screeninfo.yres > 720)
fb_data[fb1].mode_str = NULL;
else if (screeninfo.xres > 1024 &&
screeninfo.yres > 768)
fb_data[fb1].mode_str =
"800x600M-16@60";
else if (screeninfo.xres > 800 &&
screeninfo.yres > 600)
fb_data[fb1].mode_str =
"1024x768M-16@60";
} else {
/* A WVGA panel was specified and an EDID was
read thus there is a DVI monitor attached. */
if (screeninfo.xres >= 1024)
fb_data[0].mode_str = "1024x768M-16@60";
else if (screeninfo.xres >= 800)
fb_data[0].mode_str = "800x600M-16@60";
else
fb_data[0].mode_str = "640x480M-16@60";
}
}
}
#endif
return 0;
}
void __init mx51_babbage_io_init(void)
{
int i;
/* Work-around For external USB HUB chip to use default configuration
by reseting hub with i2c lines pulled low */
mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_GPIO1_7, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_GPIO1_7, 0);
if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
/* Drive I2C1 SDA line low */
mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_3, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_GPIO1_3, 0);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_3, 0);
/* Drive I2C1 SCL line low */
mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_2, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_GPIO1_2, 0);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_2, 0);
msleep(5);
mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
}
/* USB HUB RESET - De-assert USB HUB RESET_N */
msleep(1);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 0);
msleep(1);
mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 1);
for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
mxc_request_iomux(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].mux_mode);
if (mxc_iomux_pins[i].pad_cfg)
mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].pad_cfg);
if (mxc_iomux_pins[i].in_select)
mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
mxc_iomux_pins[i].in_mode);
}
mxc_set_gpio_direction(MX51_PIN_GPIO1_8, 1);
mxc_set_gpio_direction(MX51_PIN_GPIO1_0, 1); /* SD1 CD */
mxc_set_gpio_direction(MX51_PIN_GPIO1_1, 1); /* SD1 WP */
if (board_is_babbage_2_5() == 1)
/* BB2.5 */
mxc_set_gpio_direction(MX51_PIN_GPIO1_6, 1); /* SD2 CD */
else
/* BB2.0 */
mxc_set_gpio_direction(MX51_PIN_GPIO1_4, 1); /* SD2 CD */
mxc_set_gpio_direction(MX51_PIN_GPIO1_5, 1); /* SD2 WP */
/* reset FEC PHY */
mxc_set_gpio_direction(MX51_PIN_EIM_A20, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_A20, 0);
msleep(10);
mxc_set_gpio_dataout(MX51_PIN_EIM_A20, 1);
/* reset FM */
mxc_set_gpio_dataout(MX51_PIN_EIM_A21, 0);
mxc_set_gpio_direction(MX51_PIN_EIM_A21, 0);
msleep(10);
mxc_set_gpio_dataout(MX51_PIN_EIM_A21, 1);
if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
/* MX51_PIN_EIM_CRE - De-assert USB PHY RESETB */
mxc_set_gpio_direction(MX51_PIN_EIM_CRE, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_CRE, 1);
/* hphone_det_b */
mxc_set_gpio_direction(MX51_PIN_NANDF_CS0, 1);
} else {
mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);
mxc_free_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
/* i2c1 SDA */
mxc_request_iomux(MX51_PIN_EIM_D16,
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX51_PIN_EIM_D16, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* i2c1 SCL */
mxc_request_iomux(MX51_PIN_EIM_D19,
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX51_PIN_EIM_D19, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* i2c2 SDA */
mxc_request_iomux(MX51_PIN_KEY_COL5,
IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* i2c2 SCL */
mxc_request_iomux(MX51_PIN_KEY_COL4,
IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* Drive 26M_OSC_EN line high */
mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_DI1_PIN12, 0);
mxc_set_gpio_dataout(MX51_PIN_DI1_PIN12, 1);
/* Drive USB_CLK_EN_B line low */
mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_EIM_D17, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_D17, 0);
/* MX51_PIN_EIM_D21 - De-assert USB PHY RESETB */
mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D21, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_EIM_D21, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_D21, 1);
/* hphone_det_b */
mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_NANDF_D14, PAD_CTL_100K_PU);
mxc_set_gpio_direction(MX51_PIN_NANDF_D14, 1);
/* audio_clk_en_b */
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX51_PIN_CSPI1_RDY, 0);
mxc_set_gpio_dataout(MX51_PIN_CSPI1_RDY, 0);
/* power key */
mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_A27, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_NONE);
mxc_set_gpio_direction(MX51_PIN_EIM_A27, 1);
}
/* Deassert VGA reset to free i2c bus */
mxc_set_gpio_direction(MX51_PIN_EIM_A19, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_A19, 1);
/* LCD related gpio */
mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0);
}
void __init mx51_3stack_io_init(void)
{
int i, num;
struct mxc_iomux_pin_cfg *pin_ptr;
for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
mxc_request_iomux(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].mux_mode);
if (mxc_iomux_pins[i].pad_cfg)
mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].pad_cfg);
if (mxc_iomux_pins[i].in_select)
mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
mxc_iomux_pins[i].in_mode);
}
if (enable_ata) {
pin_ptr = ata_iomux_pins;
num = ARRAY_SIZE(ata_iomux_pins);
} else if (enable_sim) {
pin_ptr = sim_iomux_pins;
num = ARRAY_SIZE(sim_iomux_pins);
} else {
pin_ptr = nand_iomux_pins;
num = ARRAY_SIZE(nand_iomux_pins);
}
for (i = 0; i < num; i++) {
mxc_request_iomux(pin_ptr[i].pin, pin_ptr[i].mux_mode);
if (pin_ptr[i].pad_cfg)
mxc_iomux_set_pad(pin_ptr[i].pin, pin_ptr[i].pad_cfg);
if (pin_ptr[i].in_select)
mxc_iomux_set_input(pin_ptr[i].in_select,
pin_ptr[i].in_mode);
}
/* TO3 doesn't need pad to drive CSI_DATA_EN[0] high */
if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0)
mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT0);
/* Camera low power */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), "csi1_d8");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), 0);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), "eim_eb2");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), 0); /* TO1 */
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), 0); /* TO1 */
/* Camera reset */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), "csi1_d9");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 1);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), "gpio1_0");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); /* SD1 CD */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), "gpio1_1");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* SD1 WP */
/* EIM_D16 */
/* osc_en is shared by SPDIF */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), "eim_d16");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), 1);
/* LCD related gpio */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
/* GPS related gpio */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), "eim_cs2");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), 0);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), "eim_cre");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 1);
}
static inline void mxc_init_scc(void)
{
uint32_t reg_value;
uint32_t reg_mask = 0;
uint8_t *UMID_base;
uint32_t *MAP_base;
uint8_t i;
uint32_t partition_no;
uint32_t scc_partno;
void *scm_ram_base;
void *scc_base;
uint8_t iram_partitions = 16;
if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0)
iram_partitions = 12;
scc_base = ioremap((uint32_t) SCC_BASE_ADDR, 0x140);
if (scc_base == NULL) {
printk(KERN_ERR "FAILED TO MAP IRAM REGS\n");
return;
}
scm_ram_base = ioremap((uint32_t) IRAM_BASE_ADDR, IRAM_SIZE);
if (scm_ram_base == NULL) {
printk(KERN_ERR "FAILED TO MAP IRAM\n");
return;
}
for (partition_no = 0; partition_no < iram_partitions; partition_no++) {
/*De-allocate a Partition*/
reg_value = ((partition_no << SCM_ZCMD_PART_SHIFT) &
SCM_ZCMD_PART_MASK) | ((0x03 <<
SCM_ZCMD_CCMD_SHIFT)
& SCM_ZCMD_CCMD_MASK);
__raw_writel(reg_value, scc_base + SCM_ZCMD_REG);
msleep(1);
while ((__raw_readl(scc_base + SCM_STATUS_REG) &
SCM_STATUS_SRS_READY) != SCM_STATUS_SRS_READY) ;
/*In Supervisor mode claims a partition for it's own use
by writing zero to SMID register.*/
__raw_writel(0, scc_base + (SCM_SMID0_REG + 8 * partition_no));
reg_mask |= (3 << (2 * (partition_no)));
}
msleep(1);
reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG);
if ((reg_value & reg_mask) != reg_mask) {
printk(KERN_ERR "FAILED TO ACQUIRE IRAM PARTITION\n");
iounmap(scm_ram_base);
iounmap(scc_base);
return;
}
for (partition_no = 0; partition_no < iram_partitions; partition_no++) {
MAP_base = scm_ram_base + (partition_no * 0x2000);
UMID_base = (uint8_t *) MAP_base + 0x10;
for (i = 0; i < 16; i++)
UMID_base[i] = 0;
MAP_base[0] = SCM_PERM_NO_ZEROIZE | SCM_PERM_HD_SUP_DISABLE |
SCM_PERM_HD_READ | SCM_PERM_HD_WRITE |
SCM_PERM_TH_READ | SCM_PERM_TH_WRITE;
}
/* Freeing 2 partitions for SCC2 */
scc_partno = iram_partitions - (SCC_IRAM_SIZE / SZ_8K);
for (partition_no = scc_partno; partition_no < iram_partitions;
partition_no++) {
reg_value = ((partition_no << SCM_ZCMD_PART_SHIFT) &
SCM_ZCMD_PART_MASK) | ((0x03 <<
SCM_ZCMD_CCMD_SHIFT)
& SCM_ZCMD_CCMD_MASK);
__raw_writel(reg_value, scc_base + SCM_ZCMD_REG);
msleep(1);
while ((__raw_readl(scc_base + SCM_STATUS_REG) &
SCM_STATUS_SRS_READY) != SCM_STATUS_SRS_READY) ;
}
iounmap(scm_ram_base);
iounmap(scc_base);
printk(KERN_INFO "IRAM READY\n");
iram_ready = 1;
}
/*! MXC RTC Power management control */
static int mxc_rtc_probe(struct platform_device *pdev)
{
struct clk *clk;
struct timespec tv;
struct resource *res;
struct rtc_device *rtc;
struct rtc_drv_data *pdata = NULL;
struct mxc_srtc_platform_data *plat_data = NULL;
void __iomem *ioaddr;
void __iomem *srtc_secmode_addr;
int ret = 0;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
pdata->clk = clk_get(&pdev->dev, "rtc_clk");
clk_enable(pdata->clk);
pdata->baseaddr = res->start;
pdata->ioaddr = ioremap(pdata->baseaddr, 0x40);
ioaddr = pdata->ioaddr;
/* Configure and enable the RTC */
pdata->irq = platform_get_irq(pdev, 0);
if (pdata->irq >= 0) {
if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED,
pdev->name, pdev) < 0) {
dev_warn(&pdev->dev, "interrupt not available.\n");
pdata->irq = -1;
} else {
disable_irq(pdata->irq);
pdata->irq_enable = false;
}
}
clk = clk_get(NULL, "rtc_clk");
if (clk_get_rate(clk) != 32768) {
printk(KERN_ALERT "rtc clock is not valid");
ret = -EINVAL;
clk_put(clk);
goto err_out;
}
clk_put(clk);
/* initialize glitch detect */
__raw_writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
udelay(100);
/* clear lp interrupt status */
__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
udelay(100);;
plat_data = (struct mxc_srtc_platform_data *)pdev->dev.platform_data;
clk = clk_get(NULL, "iim_clk");
clk_enable(clk);
srtc_secmode_addr = ioremap(plat_data->srtc_sec_mode_addr, 1);
/* Check SRTC security mode */
if (((__raw_readl(srtc_secmode_addr) & SRTC_SECMODE_MASK) ==
SRTC_SECMODE_LOW) && (cpu_is_mx51_rev(CHIP_REV_1_0) == 1)) {
/* Workaround for MX51 TO1 due to inaccurate CKIL clock */
__raw_writel(SRTC_LPCR_EN_LP, ioaddr + SRTC_LPCR);
udelay(100);
} else {
/* move out of init state */
__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA),
ioaddr + SRTC_LPCR);
udelay(100);
while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0);
/* move out of non-valid state */
__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
udelay(100);
while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0);
__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
udelay(100);
}
clk_disable(clk);
clk_put(clk);
rtc = rtc_device_register(pdev->name, &pdev->dev,
&mxc_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc)) {
ret = PTR_ERR(rtc);
goto err_out;
}
pdata->rtc = rtc;
platform_set_drvdata(pdev, pdata);
tv.tv_nsec = 0;
tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR);
/* By default, devices should wakeup if they can */
/* So srtc is set as "should wakeup" as it can */
device_init_wakeup(&pdev->dev, 1);
clk_disable(pdata->clk);
return ret;
err_out:
clk_disable(pdata->clk);
iounmap(ioaddr);
if (pdata->irq >= 0)
free_irq(pdata->irq, pdev);
kfree(pdata);
return ret;
}
void __init mx51_babbage_io_init(void)
{
int i;
/* Work-around For external USB HUB chip to use default configuration
by reseting hub with i2c lines pulled low */
mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_GPIO1_7, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), "gpio1_7");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), 0);
if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
/* Drive I2C1 SDA line low */
mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_3, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), "gpio1_3");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
/* Drive I2C1 SCL line low */
mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_2, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_2), "gpio1_2");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_2), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_2), 0);
msleep(5);
mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
}
/* USB HUB RESET - De-assert USB HUB RESET_N */
msleep(1);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), 0);
msleep(1);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), 1);
for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
mxc_request_iomux(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].mux_mode);
if (mxc_iomux_pins[i].pad_cfg)
mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
mxc_iomux_pins[i].pad_cfg);
if (mxc_iomux_pins[i].in_select)
mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
mxc_iomux_pins[i].in_mode);
}
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), "gpio1_8");
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), "gpio1_0");
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), "gpio1_1");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); /* SD1 CD */
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* SD1 WP */
if (board_is_rev(BOARD_REV_2)) {
/* SD2 CD for BB2.5 */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6), "gpio1_6");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6));
} else {
/* SD2 CD for BB2.0 */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4), "gpio1_4");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4));
}
gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), "gpio1_5");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5)); /* SD2 WP */
/* reset FEC PHY */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), "eim_a20");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), 0);
msleep(10);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), 1);
/* reset FM */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), "eim_a21");
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0);
msleep(10);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 1);
if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
/* MX51_PIN_EIM_CRE - De-assert USB PHY RESETB */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), "eim_cre");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 1);
/* hphone_det_b */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), "nandf_cs0");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
} else {
mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);
mxc_free_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
/* i2c1 SDA */
mxc_request_iomux(MX51_PIN_EIM_D16,
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
INPUT_CTL_PATH0);
mxc_iomux_set_pad(MX51_PIN_EIM_D16, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* i2c1 SCL */
mxc_request_iomux(MX51_PIN_EIM_D19,
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
INPUT_CTL_PATH0);
mxc_iomux_set_pad(MX51_PIN_EIM_D19, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* i2c2 SDA */
mxc_request_iomux(MX51_PIN_KEY_COL5,
IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* i2c2 SCL */
mxc_request_iomux(MX51_PIN_KEY_COL4,
IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_ENABLE);
/* Drive 26M_OSC_EN line high */
mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), "di1_pin12");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), 1);
/* Drive USB_CLK_EN_B line low */
mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), "eim_d17");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0);
/* MX51_PIN_EIM_D21 - De-assert USB PHY RESETB */
mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D21, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D21), "eim_d21");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D21), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D21), 1);
/* hphone_det_b */
mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_NANDF_D14, PAD_CTL_100K_PU);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14), "nandf_d14");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14));
/* audio_clk_en_b */
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), "cspi1_rdy");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), 0);
/* power key */
mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_A27, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
PAD_CTL_HYS_NONE);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A27), "eim_a27");
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_A27));
}
if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) {
/* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */
mxc_request_iomux(MX51_PIN_CSI2_HSYNC, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_CSI2_HSYNC, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), "csi2_hsync");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 0);
/* TO3 doesn't need pad to drive CSI_DATA_EN[0] high */
mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT0);
}
/* Deassert VGA reset to free i2c bus */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), "eim_a19");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 1);
/* LCD related gpio */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), "di1_d0_cs");
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), "csi2_d12");
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), "csi2_d13");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 0);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), 0);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), 0);
/* Camera reset */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D23), "eim_d23");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D23), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D23), 1);
/* Camera low power */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_D19), "csi2_d19");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_D19), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D19), 0);
/* OSC_EN */
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D18), "eim_d18");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D18), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D18), 1);
if (enable_w1) {
/* OneWire */
mxc_request_iomux(MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_OWIRE_LINE, PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST |
PAD_CTL_100K_PU | PAD_CTL_PUE_PULL);
} else {
/* SPDIF Out */
mxc_request_iomux(MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT6);
mxc_iomux_set_pad(MX51_PIN_OWIRE_LINE, PAD_CTL_DRV_HIGH |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU | PAD_CTL_SRE_FAST);
}
}
