/* ------------------------------------------------------------------------*//**
* @FUNCTION voltdm_nominal_voltage_get
* @BRIEF return the nominal voltage supplied to a voltage domain.
* @RETURNS nominal voltage in micro-volt (> 0) in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in] voltdm: voltage domain name (as defined in voltdm.h)
* @DESCRIPTION return the nominal voltage supplied to a voltage domain.
* In case SmartReflex AVS Class3 is enabled,
* it may differ from the current supplied voltage.
*//*------------------------------------------------------------------------ */
int voltdm_nominal_voltage_get(const char *voltdm)
{
int id;
int uvolt;
CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG);
voltdm_init();
id = voltdm_s2id(voltdm);
if (id < 0) {
uvolt = OMAPCONF_ERR_ARG;
} else if (cpu_is_omap44xx()) {
uvolt = v2uv(voltdm44xx_nominal_voltage_get(
(voltdm44xx_id) id));
} else if (cpu_is_omap54xx()) {
uvolt = v2uv(voltdm54xx_nominal_voltage_get(
(voltdm54xx_id) id));
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
uvolt = OMAPCONF_ERR_CPU;
}
dprintf("%s(%s) = %duV\n", __func__, voltdm, uvolt);
return uvolt;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_init
* @BRIEF initialize internal data
* @DESCRIPTION initialize internal data (architecture dependent)
*//*------------------------------------------------------------------------ */
void powerdm_init(void)
{
#ifdef PWRDM_DEBUG
int i, count;
const genlist *pwrdm_list;
powerdm_info pwrdm;
#endif
if (cpu_is_omap44xx()) {
pwrdm44xx_init();
} else if (cpu_is_omap54xx()) {
pwrdm54xx_init();
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
}
#ifdef PWRDM_DEBUG
pwrdm_list = powerdm_list_get();
count = genlist_getcount((genlist *) pwrdm_list);
printf("Power Domain List:\n");
for (i = 0; i < count; i++) {
genlist_get((genlist *) pwrdm_list, i, (powerdm_info *) &pwrdm);
printf(" %s:\n", pwrdm.name);
printf(" ID:%d\n", pwrdm.id);
printf(" VoltDM: %s\n", pwrdm.voltdm);
printf(" PWRSTCTRL REG: %s\n", (pwrdm.pwrstctrl)->name);
printf(" PWRSTST REG: %s\n", (pwrdm.pwrstst)->name);
printf(" Properties: %d\n", pwrdm.properties);
printf("\n\n");
}
printf("Power Domain count: %d\n\n", count);
#endif
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION sr54xx_is_accessible
* @BRIEF check if SR module is accessible
* @RETURNS 1 if SR module is accessible, 0 otherwise
* @param[in] id: valid SR module ID
* @DESCRIPTION check if SR module is accessible
*//*------------------------------------------------------------------------ */
unsigned int sr54xx_is_accessible(sr54xx_mod_id id)
{
mod54xx_id module_id;
if (!cpu_is_omap54xx())
return 0;
switch (id) {
case SR54XX_SMARTREFLEX_MPU:
module_id = OMAP5_SMARTREFLEX_MPU;
break;
case SR54XX_SMARTREFLEX_MM:
module_id = OMAP5_SMARTREFLEX_MM;
break;
case SR54XX_SMARTREFLEX_CORE:
module_id = OMAP5_SMARTREFLEX_CORE;
break;
default:
return 0;
}
if (mod54xx_is_accessible(module_id) == 1) {
dprintf("%s(%s): SR module is accessible\n", __func__,
sr54xx_mod_name_get(id));
return 1;
} else {
dprintf("%s(%s): SR module is NOT accessible\n", __func__,
sr54xx_mod_name_get(id));
return 0;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION twl603x_is_twl6035
* @BRIEF return 1 if PMIC chip is TWL6035, 0 otherwise.
* @RETURNS 1 PMIC chip is TWL6035
* 0 otherwise
* @DESCRIPTION return 1 if PMIC chip is TWL6035, 0 otherwise.
*//*------------------------------------------------------------------------ */
unsigned short twl603x_is_twl6035(void)
{
#if 0 /* FIXME: implement true detection when ID data available */
int ret;
unsigned int val1, val2;
if (twl603x_data.chip_type != TWL603X_TYPE_MAX) {
dprintf("%s(): flag=%d\n", __func__,
(twl603x_data.chip_type == TWL6035));
return twl603x_data.chip_type == TWL6035;
}
ret = i2cget(TWL6030_I2C_BUS, 0x49, 0x02, &val2);
if (ret != 0)
goto twl603x_is_twl6035_end;
ret = i2cget(TWL6030_I2C_BUS, 0x49, 0x03, &val1);
if (ret != 0)
goto twl603x_is_twl6035_end;
if ((val1 == 0xC0) && (val2 == 0x35))
twl603x_data.chip_type = TWL6035;
twl603x_is_twl6035_end:
dprintf("%s(): val1=0x%02X val2=0x%02X flag=%d\n",
__func__, val1, val2, (twl603x_data.chip_type == TWL6035));
return twl603x_data.chip_type == TWL6035;
#else
/* FIXME: implement true detection when ID data available */
if (cpu_is_omap54xx())
return 1;
else
return 0;
#endif
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION voltdm_voltage_get
* @BRIEF return the current voltage supplied to a voltage domain.
* @RETURNS supplied voltage in micro-volt (> 0) in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_NOT_AVAILABLE
* OMAPCONF_ERR_INTERNAL
* @param[in] voltdm: voltage domain name (as defined in voltdm.h)
* @DESCRIPTION return the current voltage supplied to a voltage domain.
*//*------------------------------------------------------------------------ */
int voltdm_voltage_get(const char *voltdm)
{
int id, ret;
double volt;
CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG);
voltdm_init();
id = voltdm_s2id(voltdm);
if (id < 0)
return (double) OMAPCONF_ERR_ARG;
if (cpu_is_omap44xx()) {
ret = voltdm44xx_get_voltage((voltdm44xx_id) id, &volt);
if (ret < 0)
return (double) ret;
else
return v2uv(volt);
} else if (cpu_is_omap54xx()) {
return v2uv(voltdm54xx_voltage_get((voltdm54xx_id) id));
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return (double) OMAPCONF_ERR_CPU;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pwrdm54xx_has_last_power_state
* @BRIEF return 1 if power domain has LASTPOWERSTATEENTERED
* @RETURNS 1 if power domain has a LASTPOWERSTATEENTERED bitfield.
* 0 if not available or in case of error.
* @param[in] id: valid power domain ID
* @DESCRIPTION return 1 if power domain has LASTPOWERSTATEENTERED
* in PM_xyz_PWRSTST register (not all power domains
* feature it).
* Return 0 if not available or in case of error.
* Does not make any access to any register.
*//*------------------------------------------------------------------------ */
unsigned int pwrdm54xx_has_last_power_state(pwrdm54xx_id id)
{
unsigned int prop;
if (!cpu_is_omap54xx()) {
fprintf(stderr, "%s(): CPU != 54XX\n", __func__);
return 0;
}
if (id >= PWRDM54XX_ID_MAX) {
fprintf(stderr, "%s(): id=%u >= PWRDM54XX_ID_MAX (%u)\n",
__func__, id, PWRDM54XX_ID_MAX);
return 0;
}
prop = pwrdm54xx_properties_get(id);
if ((prop & PWRDM_HAS_LAST_STATE) != 0) {
dprintf("%s(%u): mod %s HAS LASTPOWERSTATEENTERED bitfield\n",
__func__, id, pwrdm54xx_name_get(id));
return 1;
} else {
dprintf("%s(%u): mod %s does NOT have LASTPOWERSTATEENTERED"
" bitfield\n", __func__, id, pwrdm54xx_name_get(id));
return 0;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION voltdm_s2id
* @BRIEF convert voltage domain provided as a string
* (as defined in voltdm.h) into a plaftorm-specific
* voltage domain ID (integer).
* @RETURNS plaftorm-specific voltage domain ID (> 0) if success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in] voltdm: voltage domain name (as defined in voltdm.h)
* @DESCRIPTION convert voltage domain provided as a string
* (as defined in voltdm.h) into a plaftorm-specific
* voltage domain ID (integer).
*//*------------------------------------------------------------------------ */
int voltdm_s2id(const char *voltdm)
{
CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG);
if (cpu_is_omap44xx()) {
if (strcmp(voltdm, VDD_WKUP) == 0)
return (int) OMAP4_LDO_WKUP;
else if (strcmp(voltdm, VDD_MPU) == 0)
return (int) OMAP4_VDD_MPU;
else if (strcmp(voltdm, VDD_IVA) == 0)
return (int) OMAP4_VDD_IVA;
else if (strcmp(voltdm, VDD_CORE) == 0)
return (int) OMAP4_VDD_CORE;
else
return OMAPCONF_ERR_ARG;
} else if (cpu_is_omap54xx()) {
if (strcmp(voltdm, VDD_WKUP) == 0)
return (int) VDD54XX_WKUP;
else if (strcmp(voltdm, VDD_MPU) == 0)
return (int) VDD54XX_MPU;
else if (strcmp(voltdm, VDD_MM) == 0)
return (int) VDD54XX_MM;
else if (strcmp(voltdm, VDD_CORE) == 0)
return (int) VDD54XX_CORE;
else
return OMAPCONF_ERR_ARG;
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return OMAPCONF_ERR_CPU;
}
}
static int omap2_iommu_enable(struct omap_iommu *obj)
{
u32 l, pa;
/*
* HACK: without this, we blow imprecise external abort on uEVM
* followed by L3 bus exception spew
*/
if (cpu_is_omap54xx()) {
pr_info("omap2_iommu_enable: doing Benelli reset HACK\n");
__raw_writel(3, OMAP2_L4_IO_ADDRESS(0x4AE06910));
/* We need some ugly wait here as reread or mb() are not
* sufficient... */
mdelay(500);
}
if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
return -EINVAL;
pa = virt_to_phys(obj->iopgd);
if (!IS_ALIGNED(pa, SZ_16K))
return -EINVAL;
l = iommu_read_reg(obj, MMU_REVISION);
dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
(l >> 4) & 0xf, l & 0xf);
iommu_write_reg(obj, pa, MMU_TTB);
__iommu_set_twl(obj, true);
return 0;
}
/**
* omap4_opp_init() - initialize omap4 opp table
*/
static int __init omap5_opp_init(void)
{
int r = -ENODEV;
pr_info("Registering %d OPPs\n", ARRAY_SIZE(omap54xx_opp_def_list));
if (!cpu_is_omap54xx())
return r;
r = omap_init_opp_table(omap54xx_opp_def_list,
ARRAY_SIZE(omap54xx_opp_def_list));
if (!cpu_is_omap5432()) {
/* Enable scaling on the Core domain */
struct omap_hwmod *oh_mpu = omap_hwmod_lookup("l3_main_1");
struct platform_device *pdev;
if (!oh_mpu || !oh_mpu->od) {
return r;
} else {
pdev = oh_mpu->od->pdev;
r = opp_enable(&pdev->dev, 133000000);
if (r < 0) {
dev_err(&pdev->dev,
"unable to enable Core LOW OPP for 5430 device!\n");
return r;
}
}
pr_info("Added LOW OPP to CORE domain - this is expected on 5430 device\n");
} else {
pr_info("Did not LOW OPP to CORE domain - this is expected on 5432 device\n");
}
return r;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pwrdm54xx_has_logic_ret_state_ctrl_bit
* @BRIEF return 1 if power domain has LOGICRETSTATE bitfield
* @RETURNS 1 if power domain has a LOGICRETSTATE bitfield.
* 0 if not available or in case of error.
* @param[in] id: valid power domain ID
* @DESCRIPTION return 1 if power domain has LOGICRETSTATE bitfield
* in PM_xyz_PWRSTCTRL register (not all power domains
* feature it).
* Return 0 if not available or in case of error.
* Does not make any access to any register.
*//*------------------------------------------------------------------------ */
unsigned int pwrdm54xx_has_logic_ret_state_ctrl_bit(pwrdm54xx_id id)
{
unsigned int prop;
if (!cpu_is_omap54xx()) {
fprintf(stderr, "%s(): CPU != 54XX\n", __func__);
return 0;
}
if (id >= PWRDM54XX_ID_MAX) {
fprintf(stderr, "%s(): id=%u >= PWRDM54XX_ID_MAX (%u)\n",
__func__, id, PWRDM54XX_ID_MAX);
return 0;
}
prop = pwrdm54xx_properties_get(id);
if ((prop & PWRDM_HAS_LOGIC_RET_STATE_CTRL_BIT) != 0) {
dprintf("%s(%u): mod %s HAS LOGICRETSTATE bitfield\n",
__func__, id, pwrdm54xx_name_get(id));
return 1;
} else {
dprintf("%s(%u): mod %s does NOT have LOGICRETSTATE"
" bitfield\n", __func__, id, pwrdm54xx_name_get(id));
return 0;
}
}
/**
* usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
* @pdev: USB Host Controller being removed
*
* Reverses the effect of usbhs_omap_probe().
*/
static int __devexit usbhs_omap_remove(struct platform_device *pdev)
{
struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
omap_usbhs_deinit(&pdev->dev);
iounmap(omap->uhh_base);
clk_put(omap->usb_host_hs_hsic480m_p2_clk);
clk_put(omap->usb_host_hs_hsic60m_p2_clk);
clk_put(omap->usb_host_hs_hsic480m_p1_clk);
clk_put(omap->usb_host_hs_hsic60m_p1_clk);
clk_put(omap->init_60m_fclk);
clk_put(omap->usbhost_p2_fck);
clk_put(omap->usbhost_p1_fck);
clk_put(omap->xclk60mhsp2_ck);
clk_put(omap->utmi_p2_fck);
clk_put(omap->xclk60mhsp1_ck);
clk_put(omap->utmi_p1_fck);
clk_put(omap->ehci_logic_fck);
if (cpu_is_omap54xx()) {
clk_put(omap->usbhost_p3_fck);
clk_put(omap->usb_host_hs_hsic480m_p3_clk);
clk_put(omap->usb_host_hs_hsic60m_p3_clk);
}
pm_runtime_disable(&pdev->dev);
kfree(omap);
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION voltdm_por_nominal_voltage_get
* @BRIEF return the nominal voltage to be supplied to a
* voltage domain, as defined in Data Manual.
* @RETURNS nominal voltage in micro-volt (> 0) in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in] voltdm: voltage domain name (as defined in voltdm.h)
* @param[in] opp: OPP provided as a string (as defined in opp.h)
* @DESCRIPTION return the nominal voltage to be supplied to a
* voltage domain, as defined in Data Manual.
* Not read from the platform, but from internal tables.
*//*------------------------------------------------------------------------ */
int voltdm_por_nominal_voltage_get(const char *voltdm, const char *opp)
{
int vdd_id, opp_id;
CHECK_NULL_ARG(voltdm, OMAPCONF_ERR_ARG);
voltdm_init();
vdd_id = voltdm_s2id(voltdm);
if (vdd_id < 0)
return OMAPCONF_ERR_ARG;
opp_id = opp_s2id(opp);
if (opp_id < 0)
return opp_id;
if (cpu_is_omap44xx()) {
return v2uv(voltdm44xx_por_nominal_voltage_get(
(voltdm44xx_id) vdd_id, (opp44xx_id) opp_id));
} else if (cpu_is_omap54xx()) {
return v2uv(voltdm54xx_por_nominal_voltage_get(
(voltdm54xx_id) vdd_id, (opp54xx_id) opp_id));
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return OMAPCONF_ERR_CPU;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION twl603x_main
* @BRIEF TWL603x menu
* ### DEPRECATED, DO NOT USE ANYMORE ###
* @RETURNS 0 in case of success
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_INTERNAL
* @param[in] argc: shell input argument number
* @param[in] argv: shell input argument(s)
* @DESCRIPTION TWL603x menu
* ### DEPRECATED, DO NOT USE ANYMORE ###
*//*------------------------------------------------------------------------ */
int twl603x_main(int argc, char *argv[])
{
int ret;
if (!cpu_is_omap44xx() && !cpu_is_omap54xx())
return OMAPCONF_ERR_CPU;
if (argc == 2) {
static unsigned char init_done = 0;
if (!init_done) {
twl603x_init_regtable();
init_done = 1;
}
if (strcmp(argv[1], "dump") == 0)
ret = twl603x_dumpregs(stdout);
else if (cpu_is_omap54xx())
ret = OMAPCONF_ERR_ARG;
else if (strcmp(argv[1], "cfg") == 0)
ret = twl603x_config(stdout);
else if (strcmp(argv[1], "ldocfg") == 0)
ret = twl603x_config_ldo(stdout);
else if (strcmp(argv[1], "smpscfg") == 0)
ret = twl603x_config_smps(stdout);
else if (strcmp(argv[1], "rescfg") == 0)
ret = twl603x_config_resources(stdout);
else if (strcmp(argv[1], "devpwrgrpstat") == 0)
ret = twl603x_config_devpwrgrp_status(stdout);
else if (strcmp(argv[1], "reset") == 0)
ret = twl603x_reset(stdout);
else
ret = OMAPCONF_ERR_ARG;
} else if (argc == 4) {
if (strcmp(argv[1], "setpwrgrp") == 0) {
ret = twl603x_pwrgrp_set(stdout, argv[2], argv[3]);
} else {
ret = OMAPCONF_ERR_ARG;
}
} else {
ret = OMAPCONF_ERR_ARG;
}
if (ret == OMAPCONF_ERR_ARG)
help(HELP_PMIC);
return ret;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pwrdm54xx_has_pwrstst_reg
* @BRIEF return 1 if power domain features PM_xyz_PWRSTST,
* 0 otherwise.
* @RETURNS 1 if power domain features PM_xyz_PWRSTST register
* 0 otherwise
* @param[in] id: valid power domain ID
* @DESCRIPTION return 1 if power domain features PM_xyz_PWRSTST,
* 0 otherwise.
*//*------------------------------------------------------------------------ */
unsigned int pwrdm54xx_has_pwrstst_reg(pwrdm54xx_id id)
{
if (!cpu_is_omap54xx())
return 0;
CHECK_ARG_LESS_THAN(id, PWRDM54XX_ID_MAX, 0);
return (pwrdm54xx_pwrstst_table[id] != NULL);
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pwrdm54xx_pwrstst_reg_get
* @BRIEF return pointer to power domain PM_xyz_PWRSTST register.
* @RETURNS pointer to power domain PM_xyz_PWRSTST register
* NULL in case of error
* @param[in] id: valid power domain ID
* @DESCRIPTION return pointer to power domain PM_xyz_PWRSTST register.
*//*------------------------------------------------------------------------ */
reg *pwrdm54xx_pwrstst_reg_get(pwrdm54xx_id id)
{
if (!cpu_is_omap54xx())
return NULL;
CHECK_ARG_LESS_THAN(id, PWRDM54XX_ID_MAX, NULL);
return pwrdm54xx_pwrstst_table[id];
}
static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
struct hdmi_pll_info *pi)
{
unsigned long clkin, refclk;
u32 mf;
clkin = clk_get_rate(hdmi.sys_clk) / 10000;
/*
* Input clock is predivided by N + 1
* out put of which is reference clk
*/
if (dssdev->clocks.hdmi.regn == 0)
pi->regn = HDMI_DEFAULT_REGN;
else
pi->regn = dssdev->clocks.hdmi.regn;
refclk = clkin / pi->regn;
if (dssdev->clocks.hdmi.regm2 == 0) {
if (cpu_is_omap44xx()) {
pi->regm2 = HDMI_DEFAULT_REGM2;
} else if (cpu_is_omap54xx()) {
if (phy <= 50000)
pi->regm2 = 2;
else
pi->regm2 = 1;
}
} else {
pi->regm2 = dssdev->clocks.hdmi.regm2;
}
/*
* multiplier is pixel_clk/ref_clk
* Multiplying by 100 to avoid fractional part removal
*/
pi->regm = phy * pi->regm2 / refclk;
/*
* fractional multiplier is remainder of the difference between
* multiplier and actual phy(required pixel clock thus should be
* multiplied by 2^18(262144) divided by the reference clock
*/
mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
pi->regmf = pi->regm2 * mf / refclk;
/*
* Dcofreq should be set to 1 if required pixel clock
* is greater than 1000MHz
*/
pi->dcofreq = phy > 1000 * 100;
pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
/* Set the reference clock to sysclk reference */
pi->refsel = HDMI_REFSEL_SYSCLK;
DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
}
void omapconf_emu_disable_domain()
{
if (cpu_is_omap44xx())
//omap4conf_emu_disable_domain();
mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0);
else if (cpu_is_omap54xx())
//omap5conf_emu_disable_domain();
mem_write(OMAP5430_CM_L3INSTR_L3_MAIN_3_CLKCTRL, 0x0);
}
static u32 __init omap_hsmmc_si_spec_caps2(struct omap2_hsmmc_info *c)
{
u32 caps2 = 0;
if (cpu_is_omap54xx()) {
if (c->mmc == 2) {
caps2 |= MMC_CAP2_HS200_1_8V_SDR;
}
}
return caps2;
}
/*
* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
* ROM code. WakeupGen IP is integrated along with GIC to manage the
* interrupt wakeups from CPU low power states. It manages
* masking/unmasking of Shared peripheral interrupts(SPI). So the
* interrupt enable/disable control should be in sync and consistent
* at WakeupGen and GIC so that interrupts are not lost.
*/
static void irq_save_context(void)
{
if (!sar_base)
sar_base = omap4_get_sar_ram_base();
if (cpu_is_omap54xx())
omap5_irq_save_context();
else
omap4_irq_save_context();
}
static int __init
omap_hsmmc_max_min(u8 slot, unsigned long *max, unsigned long *min)
{
if (cpu_is_omap54xx()) {
switch (slot) {
case 0:
case 1:
*max = 192000000;
break;
case 2:
case 3:
case 4:
*max = 48000000;
break;
default:
return -EINVAL;
}
} else if (cpu_is_omap44xx()) {
switch (slot) {
case 0:
case 1:
*max = 96000000;
break;
case 2:
case 3:
case 4:
*max = 48000000;
break;
default:
return -EINVAL;
}
} else if (cpu_is_omap34xx()) {
switch (slot) {
case 0:
case 1:
case 2:
*max = 96000000;
break;
default:
return -EINVAL;
}
} else if (cpu_is_omap24xx()) {
switch (slot) {
case 0:
case 1:
*max = 96000000;
break;
default:
return -EINVAL;
}
} else
return -EINVAL;
*min = 40000;
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION mem_map_32k
* @BRIEF map given physical address
* @RETURNS 32K virtual address
* @DESCRIPTION map given physical address
*//*------------------------------------------------------------------------ */
volatile unsigned int *mem_map_32k(void)
{
unsigned int reg_32k;
if (cpu_is_omap54xx() || cpu_is_dra7xx())
reg_32k = OMAP5430_CR;
else if (cpu_is_omap44xx())
reg_32k = T32KSYNCNT_CR;
return mem_map_address(reg_32k);
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION cpu_cores_count_get
* @BRIEF return the number of CPU cores available
* @RETURNS >0 number of CPU cores available
* 0 in case of error (unknown architecture)
* @param[in] none
* @DESCRIPTION return the number of CPU cores available
*//*------------------------------------------------------------------------ */
unsigned int cpu_cores_count_get(void)
{
FILE *fp;
char line[256];
if (cpu_cores_count != -1)
return cpu_cores_count;
if (cpu_is_omap44xx()) {
cpu_cores_count = cpu44xx_cores_count_get();
} else if (cpu_is_omap54xx()) {
cpu_cores_count = cpu54xx_cores_count_get();
} else {
/* Open "/proc/stat" file */
fp = fopen("/proc/stat", "r");
if (fp == NULL) {
dprintf("%s(%u): error opening %s file!\n",
__func__, cpu, "/proc/stat");
fprintf(stderr,
"omapconf (%s()): could not retrieve the number of CPU cores !\n",
__func__);
cpu_cores_count = 0;
return (unsigned int) cpu_cores_count;
}
/* /proc/stat is formatted like this:
* cpu 6982 2624 19577 7242532 12176 0 868 0 0 0
* cpu0 3960 1682 9120 1796241 9116 0 837 0 0 0
* cpu1 1616 837 6133 1810747 1614 0 16 0 0 0
* cpu2 1068 88 2574 1816656 949 0 14 0 0 0
* cpu3 337 15 1748 1818886 496 0 0 0 0 0
* ...
* intr 1676733 49 1773 0 0 0 0 0 0 0 0 0 0 1032 0 0 45427 0 0
* ...
*/
cpu_cores_count = -1;
if (fgets(line, sizeof(line), fp)) {
dprintf("unexpected read\n");
}
while ((line != NULL) && (strstr(line, "cpu") != NULL)) {
cpu_cores_count++;
if (fgets(line, sizeof(line), fp)) {
dprintf("unexpected read\n");
}
};
dprintf("%s(): cpu_cores_count=%u\n", __func__,
cpu_cores_count);
/* Close file */
fclose(fp);
}
return (unsigned int) cpu_cores_count;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION opp_deinit
* @BRIEF free dynamically allocated internal data.
* @DESCRIPTION free dynamically allocated internal data.
* MUST BE CALLED AT END OF EXECUTION.
*//*------------------------------------------------------------------------ */
void opp_deinit(void)
{
if (cpu_is_omap44xx()) {
opp44xx_deinit();
} else if (cpu_is_omap54xx()) {
opp54xx_deinit();
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
}
}
/**
* omap4_emif_set_device_details() - Pass DDR device details from board file
* @emif_nr: The EMIF instance on which device is attached
* @device_info: Device info such as type, bus width, density etc.
* @timings: Timings information from device datasheet passed
* as an array of 'struct lpddr2_timings'. Can be NULL
* if if default timings are ok.
* @timings_arr_size: Size of the timings array. Depends on the number
* of different frequencies for which timings data
* is provided.
* @min_tck: Minimum value of some timing parameters in terms
* of number of cycles. Can be NULL if default values
* are ok.
*
* This function shall be used by the OMAP board files to pass DDR device
* device information to the EMIF driver. It will in turn create EMIF
* platform devices and pass the DDR device data and HW capability information
* to the EMIF driver through platform data.
*/
void __init omap_emif_set_device_details(u32 emif_nr,
struct ddr_device_info *device_info,
struct lpddr2_timings *timings,
u32 timings_arr_size,
struct lpddr2_min_tck *min_tck,
struct emif_custom_configs *custom_configs)
{
struct platform_device *pd;
struct omap_hwmod *oh;
char oh_name[10];
if (emif_nr > 2 || !device_info)
goto error;
if (cpu_is_omap44xx()) {
omap_emif_platform_data.ip_rev = EMIF_4D;
omap_emif_platform_data.phy_type = EMIF_PHY_TYPE_ATTILAPHY;
} else if (cpu_is_omap54xx()) {
omap_emif_platform_data.ip_rev = EMIF_4D5;
omap_emif_platform_data.phy_type = EMIF_PHY_TYPE_INTELLIPHY;
} else {
goto error;
}
sprintf(oh_name, "emif%d", emif_nr);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("EMIF: could not find hwmod device %s\n", oh_name);
return;
}
omap_emif_platform_data.device_info = device_info;
omap_emif_platform_data.timings = timings;
omap_emif_platform_data.min_tck = min_tck;
omap_emif_platform_data.timings_arr_size = timings_arr_size;
omap_emif_platform_data.custom_configs = custom_configs;
oh = omap_hwmod_lookup(oh_name);
if (!oh)
goto error;
pd = omap_device_build("emif", emif_nr, oh,
&omap_emif_platform_data,
sizeof(omap_emif_platform_data),
NULL, 0, false);
if (!pd)
goto error;
return;
error:
pr_err("OMAP: EMIF device generation failed for EMIF%u\n", emif_nr);
return;
}
/*
* Clear WakeupGen SAR backup status.
*/
static void irq_sar_clear(void)
{
u32 val;
u32 offset = SAR_BACKUP_STATUS_OFFSET;
if (cpu_is_omap54xx())
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
val = __raw_readl(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + offset);
}
static int __init secure_pm_init(void)
{
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
cpu_pm_register_notifier(&secure_notifier_block);
if (cpu_is_omap44xx())
ppa_service_0_index = OMAP4_PPA_SERVICE_0;
else if (cpu_is_omap54xx())
ppa_service_0_index = OMAP5_PPA_SERVICE_0;
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION opp_s2id
* @BRIEF convert OPP provided as a string (as defined in opp.h)
* into a plaftorm-specific OPP ID (integer).
* @RETURNS plaftorm-specific OPP ID (> 0) in case of success
* OMAPCONF_ERR_CPU
* @param[in] opp: OPP provided as a string (as defined in opp.h)
* @DESCRIPTION convert OPP provided as a string (as defined in opp.h)
* into a plaftorm-specific OPP ID (integer).
*//*------------------------------------------------------------------------ */
int opp_s2id(const char *opp)
{
if (cpu_is_omap44xx()) {
return opp44xx_id_get(opp);
} else if (cpu_is_omap54xx()) {
return opp54xx_id_get(opp);
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return OMAPCONF_ERR_CPU;
}
}
int __init omap_init_clocksource_32k(void)
{
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
u32 pbase;
unsigned long size = SZ_4K;
void __iomem *base;
struct clk *sync_32k_ick;
if (cpu_is_omap16xx()) {
pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
size = SZ_1K;
} else if (cpu_is_omap2420())
pbase = OMAP2420_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap2430())
pbase = OMAP2430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap34xx())
pbase = OMAP3430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap44xx())
pbase = OMAP4430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap54xx())
pbase = OMAP54XX_32KSYNCT_BASE + 0x30;
else
return -ENODEV;
/* For this to work we must have a static mapping in io.c for this area */
base = ioremap(pbase, size);
if (!base)
return -ENODEV;
sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
if (!IS_ERR(sync_32k_ick))
clk_enable(sync_32k_ick);
timer_32k_base = base;
/*
* 120000 rough estimate from the calculations in
* __clocksource_updatefreq_scale.
*/
clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
32768, NSEC_PER_SEC, 120000);
if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
clocksource_mmio_readl_up))
printk(err, "32k_counter");
setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
}
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION voltdm_list_get
* @BRIEF return the list of voltage domain(s)
* @RETURNS list of voltage domain(s) in case of success
* NULL if not available
* @DESCRIPTION return the number of voltage domain(s)
*//*------------------------------------------------------------------------ */
const genlist *voltdm_list_get(void)
{
voltdm_init();
if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
return (const genlist *) &voltdm_list;
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return NULL;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION voltdm_count_get
* @BRIEF return the number of voltage domain(s)
* @RETURNS number of voltage domain(s) (> 0) in case of success
* OMAPCONF_ERR_CPU
* @DESCRIPTION return the number of voltage domain(s)
*//*------------------------------------------------------------------------ */
int voltdm_count_get(void)
{
if (cpu_is_omap44xx()) {
return (int) OMAP4_VD_ID_MAX;
} else if (cpu_is_omap54xx()) {
return (int) VDD54XX_ID_MAX;
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return OMAPCONF_ERR_CPU;
}
}
