Esempio n. 1
0
static int get_vendor(void){
  int eax, ebx, ecx, edx;

  union
  {
        char vchar[16];
        int  vint[4];
  } vendor;

  cpuid(0, &eax, &ebx, &ecx, &edx);

  *(&vendor.vint[0]) = ebx;
  *(&vendor.vint[1]) = edx;
  *(&vendor.vint[2]) = ecx;

  vendor.vchar[12] = '\0';

  if (!strcmp(vendor.vchar, "GenuineIntel")) return VENDOR_INTEL;
  if (!strcmp(vendor.vchar, "AuthenticAMD")) return VENDOR_AMD;
  if (!strcmp(vendor.vchar, "CentaurHauls")) return VENDOR_CENTAUR;

  if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;

  return VENDOR_UNKNOWN;
}
Esempio n. 2
0
static void cpuid_smp_cpuid(void *cmd_block)
{
	struct cpuid_command *cmd = (struct cpuid_command *)cmd_block;

	cpuid(cmd->reg, &cmd->data[0], &cmd->data[1], &cmd->data[2],
		      &cmd->data[3]);
}
Esempio n. 3
0
int get_vendor(void){
  int eax, ebx, ecx, edx;
  char vendor[13];

  cpuid(0, &eax, &ebx, &ecx, &edx);
  
  *(int *)(&vendor[0]) = ebx;
  *(int *)(&vendor[4]) = edx;
  *(int *)(&vendor[8]) = ecx;
  vendor[12] = (char)0;

  if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
  if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
  if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
  if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
  if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
  if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
  if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
  if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
  if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
  if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;

  if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;

  return VENDOR_UNKNOWN;
}
Esempio n. 4
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static __inline__ int get_l3_size(void){

  int eax, ebx, ecx, edx;

  cpuid(0x80000006, &eax, &ebx, &ecx, &edx);

  return BITMASK(edx, 18, 0x3fff) * 512;
}
Esempio n. 5
0
static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit) {
    int got_intel_cpu=0;
    unsigned int reg[5]; 
    
    reg[4] = '\0' ;
    cpuid(reg, 0, 0);  
    if(XMEMCMP((char *)&(reg[EBX]), "Genu", 4) == 0 &&  
                XMEMCMP((char *)&(reg[EDX]), "ineI", 4) == 0 &&  
                XMEMCMP((char *)&(reg[ECX]), "ntel", 4) == 0) {  
        got_intel_cpu = 1;  
    }    
    if (got_intel_cpu) {
        cpuid(reg, leaf, sub);
        return((reg[num]>>bit)&0x1) ;
    }
    return 0 ;
}
Esempio n. 6
0
static void cpuid_init( ) {
    if (!cpuid_done) {
        cpuid(0x1, cpuid_ecx, cpuid_edx);
        cpuid_done = true;

        print_cpu_info( );
    }
}
Esempio n. 7
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static void cpuid_smp_cpuid(void *cmd_block)
{
	struct cpuid_command *cmd = (struct cpuid_command *)cmd_block;

	if (cmd->cpu == smp_processor_id())
		cpuid(cmd->reg, &cmd->data[0], &cmd->data[1], &cmd->data[2],
		      &cmd->data[3]);
}
void slave_main(void)
{
	send(MSIM_MASTER_ID, 0, 4);
	set_trap_handler();
	tlb_init();
	kprintf("--DEBUG-- Hello world from CPU #%d!\n", cpuid());
	for (;;);
}
Esempio n. 9
0
/*
 * is_cpu_clflush_present -- checks if CLFLUSH instruction is supported
 */
int is_cpu_clflush_present(void) {
  unsigned cpuinfo[4] = {0};

  cpuid(0x1, 0x0, cpuinfo);

  int ret = (cpuinfo[EDX_IDX] & bit_CLFLUSH) != 0;

  return ret;
}
Esempio n. 10
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inline static bool is_sse2_available()
{
#if (defined(__x86_64__) || defined(__amd64))
    return true;
#endif
    int a,b,c,d;
        cpuid(1, a, b, c, d);
    return d & (1<<26); // edx bit 26 is set when SSE2 is present
        }
Esempio n. 11
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static int core2_get_pmc_count(void)
{
    u32 eax, ebx, ecx, edx;

    if ( arch_pmc_cnt == 0 )
    {
        cpuid(0xa, &eax, &ebx, &ecx, &edx);
        arch_pmc_cnt = (eax & 0xff00) >> 8;
    }
Esempio n. 12
0
inline
cpu_info::
cpu_info()
{
    constexpr std::uint32_t SSE42 = 1 << 20;

    std::uint32_t eax = 0;
    std::uint32_t ebx = 0;
    std::uint32_t ecx = 0;
    std::uint32_t edx = 0;

    cpuid(0, eax, ebx, ecx, edx);
    if(eax >= 1)
    {
        cpuid(1, eax, ebx, ecx, edx);
        sse42 = (ecx & SSE42) != 0;
    }
}
Esempio n. 13
0
ogg_uint32_t oc_cpu_flags_get(void){
  ogg_uint32_t flags;
  ogg_uint32_t eax;
  ogg_uint32_t ebx;
  ogg_uint32_t ecx;
  ogg_uint32_t edx;
# if !defined(__amd64__)&&!defined(__x86_64__)
  /*Not all x86-32 chips support cpuid, so we have to check.*/
  __asm__ __volatile__(
   "pushfl\n\t"
   "pushfl\n\t"
   "popl %[a]\n\t"
   "movl %[a],%[b]\n\t"
   "xorl $0x200000,%[a]\n\t"
   "pushl %[a]\n\t"
   "popfl\n\t"
   "pushfl\n\t"
   "popl %[a]\n\t"
   "popfl\n\t"
   :[a]"=r"(eax),[b]"=r"(ebx)
   :
   :"cc"
  );
  /*No cpuid.*/
  if(eax==ebx)return 0;
# endif
  cpuid(0,eax,ebx,ecx,edx);
  /*         l e t n          I e n i          u n e G*/
  if(ecx==0x6C65746E&&edx==0x49656E69&&ebx==0x756E6547||
   /*      6 8 x M          T e n i          u n e G*/
   ecx==0x3638784D&&edx==0x54656E69&&ebx==0x756E6547){
    int family;
    int model;
    /*Intel, Transmeta (tested with Crusoe TM5800):*/
    cpuid(1,eax,ebx,ecx,edx);
    flags=oc_parse_intel_flags(edx,ecx);
    family=(eax>>8)&0xF;
    model=(eax>>4)&0xF;
    /*The SSE unit on the Pentium M and Core Duo is much slower than the MMX
       unit, so don't use it.*/
    if(family==6&&(model==9||model==13||model==14)){
      flags&=~(OC_CPU_X86_SSE2|OC_CPU_X86_PNI);
    }
  }
Esempio n. 14
0
void cpu_info()
{
   char idstr[64];
   idstr[0] = 0;

   fillCpuString(idstr);

   trim(idstr);

   unsigned cpuver = cpuid(1,0);
   unsigned features = cpuid(1,1);
   temp.mmx = (features >> 23) & 1;
   temp.sse = (features >> 25) & 1;
   temp.sse2 = (features >> 26) & 1;

   temp.cpufq = GetCPUFrequency();

   color(CONSCLR_HARDITEM); printf("cpu: ");

   color(CONSCLR_HARDINFO);
   printf("%s ", idstr);

   color(CONSCLR_HARDITEM);
   printf("%d.%d.%d [MMX:%s,SSE:%s,SSE2:%s] ",
      (cpuver>>8) & 0x0F, (cpuver>>4) & 0x0F, cpuver & 0x0F,
      temp.mmx ? "YES" : "NO",
      temp.sse ? "YES" : "NO",
      temp.sse2 ? "YES" : "NO");

   color(CONSCLR_HARDINFO);
   printf("at %d MHz\n", (unsigned)(temp.cpufq/1000000));

#ifdef MOD_SSE2
   if (!temp.sse2) {
      color(CONSCLR_WARNING);
      printf("warning: this is an SSE2 build, recompile or download non-P4 version\n");
   }
#else //MOD_SSE2
   if (temp.sse2) {
      color(CONSCLR_WARNING);
      printf("warning: SSE2 disabled in compile-time, recompile or download P4 version\n");
   }
#endif
}
Esempio n. 15
0
static void __init setup_boot_cpu_data(void)
{
	int dummy, eax;

	/* get vendor info */
	cpuid(0, &boot_cpu_data.cpuid_level,
	      (int *)&boot_cpu_data.x86_vendor_id[0],
	      (int *)&boot_cpu_data.x86_vendor_id[8],
	      (int *)&boot_cpu_data.x86_vendor_id[4]);

	/* get cpu type */
	cpuid(1, &eax, &dummy, &dummy, (int *) &boot_cpu_data.x86_capability);
	boot_cpu_data.x86 = (eax >> 8) & 0xf;
	boot_cpu_data.x86_model = (eax >> 4) & 0xf;
	boot_cpu_data.x86_mask = eax & 0xf;

	/* Also determine cpu vendor */
	get_cpu_vendor(&boot_cpu_data);
}
Esempio n. 16
0
static void
calibrate_tsc(void)
{
if (0) {
    u32 eax, ebx, ecx, edx, cpuid_features = 0;
    cpuid(0, &eax, &ebx, &ecx, &edx);
    if (eax > 0)
        cpuid(1, &eax, &ebx, &ecx, &cpuid_features);

    if (!(cpuid_features & CPUID_TSC)) {
        SET_GLOBAL(no_tsc, 1);
        SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000);
        dprintf(3, "386/486 class CPU. Using TSC emulation\n");
        return;
    }

    // Setup "timer2"
    u8 orig = inb(PORT_PS2_CTRLB);
    outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
    /* binary, mode 0, LSB/MSB, Ch 2 */
    outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
    /* LSB of ticks */
    outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
    /* MSB of ticks */
    outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);

    u64 start = rdtscll();
    while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
        ;
    u64 end = rdtscll();

    // Restore PORT_PS2_CTRLB
    outb(orig, PORT_PS2_CTRLB);

    // Store calibrated cpu khz.
    u64 diff = end - start;
    dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
            , (u32)start, (u32)end, (u32)diff);
    u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
    SET_GLOBAL(cpu_khz, hz / 1000);

    dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
}
Esempio n. 17
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int
arch_support_sse2(void)
{
    unsigned int eax, ebx, ecx, edx;

    cpuid(1, &eax, &ebx, &ecx, &edx);

    /* Return non-zero if SSE2 is supported */
    return edx & 0x4000000;
}
Esempio n. 18
0
File: save.c Progetto: amodj/Utopia
void arch_hvm_save(struct domain *d, struct hvm_save_header *hdr)
{
    uint32_t eax, ebx, ecx, edx;

    /* Save some CPUID bits */
    cpuid(1, &eax, &ebx, &ecx, &edx);
    hdr->cpuid = eax;

    hdr->pad0 = 0;
}
Esempio n. 19
0
int DST_InitDecoder(ebunch * D, int NrOfChannels, int SampleRate) 
{
  int  retval = 0;

  memset(D, 0, sizeof(ebunch));

  D->FrameHdr.NrOfChannels   = NrOfChannels;
  /*  64FS =>  4704 */
  /* 128FS =>  9408 */
  /* 256FS => 18816 */
  D->FrameHdr.MaxFrameLen    = (588 * SampleRate / 8); 
  D->FrameHdr.ByteStreamLen  = D->FrameHdr.MaxFrameLen   * D->FrameHdr.NrOfChannels;
  D->FrameHdr.BitStreamLen   = D->FrameHdr.ByteStreamLen * RESOL;
  D->FrameHdr.NrOfBitsPerCh  = D->FrameHdr.MaxFrameLen   * RESOL;
  D->FrameHdr.MaxNrOfFilters = 2 * D->FrameHdr.NrOfChannels;
  D->FrameHdr.MaxNrOfPtables = 2 * D->FrameHdr.NrOfChannels;

  D->FrameHdr.FrameNr = 0;
  D->StrFilter.TableType = FILTER;
  D->StrPtable.TableType = PTABLE;

  if (retval==0) 
  {
    AllocateDecMemory(D);
  }

  if (retval==0) 
  {
    retval = CCP_CalcInit(&D->StrFilter);
  }
  if (retval==0) 
  {
    retval = CCP_CalcInit(&D->StrPtable);
  }

  D->SSE2 = 0;
#if !defined(NO_SSE2) && (defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__x86_64__))
  {
    int CPUInfo[4];
#if defined(__i386__) || defined(__x86_64__)
#define cpuid(type, a, b, c, d) \
    __asm__ ("cpuid":\
    "=a" (a), "=b" (b), "=c" (c), "=d" (d) : "a" (type));

    cpuid(1, CPUInfo[0], CPUInfo[1], CPUInfo[2], CPUInfo[3]);
#else
    __cpuid(CPUInfo, 1);
#endif

    D->SSE2 = (CPUInfo[3] & (1L << 26)) ? 1 : 0;
  }
#endif

  return(retval);
}
  // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
  address generate_getPsrInfo() {
    StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
#   define __ _masm->

    address start = __ pc();

    // rbx is callee-save on both unix and windows
    // rcx and rdx are first and second argument registers on windows

    __ pushq(rbx);
    __ movq(r8, rarg0);

    __ xorl(rax, rax);
    __ cpuid();
    __ leaq(r9, Address(r8, in_bytes(VM_Version::std_cpuid0_offset())));
    __ movl(Address(r9, 0),  rax);
    __ movl(Address(r9, 4),  rbx);
    __ movl(Address(r9, 8),  rcx);
    __ movl(Address(r9, 12), rdx);

    __ movl(rax, 1);
    __ cpuid();
    __ leaq(r9, Address(r8, in_bytes(VM_Version::std_cpuid1_offset())));
    __ movl(Address(r9, 0),  rax);
    __ movl(Address(r9, 4),  rbx);
    __ movl(Address(r9, 8),  rcx);
    __ movl(Address(r9, 12), rdx);

    __ movl(rax, 0x80000001);
    __ cpuid();
    __ leaq(r9, Address(r8, in_bytes(VM_Version::ext_cpuid1_offset())));
    __ movl(Address(r9, 0),  rax);
    __ movl(Address(r9, 4),  rbx);
    __ movl(Address(r9, 8),  rcx);
    __ movl(Address(r9, 12), rdx);

    __ popq(rbx);

    __ ret(0);

    return start;
  }
Esempio n. 21
0
/*
 * is_cpu_pcommit_present -- checks if PCOMMIT instruction is supported
 */
int is_cpu_pcommit_present(void) {
  unsigned cpuinfo[4] = {0};

  if (!is_cpu_genuine_intel()) return 0;

  cpuid(0x7, 0x0, cpuinfo);

  int ret = (cpuinfo[EBX_IDX] & bit_PCOMMIT) != 0;

  return ret;
}
Esempio n. 22
0
int cpuid_PMC_num()
{
	uint32_t eax, ebx, ecx, edx;
	int leaf = 10; // 0A
	cpuid(leaf, &eax, &ebx, &ecx, &edx);
	return MASK_VAL(eax, 15, 8);		// This value tells which PMC's are available
						// If it is > 3 then up to PMC3 is usable
						// ...
						// If	    > 0 then PMC0 is usable
						// If == 0, then none are usable
}
Esempio n. 23
0
int main(int argc, char **argv)
{
        unsigned long eax, ebx, ecx, edx;

        cpuid(0);
        printf("identification: \"%.4s%.4s%.4s\"\n", (char *)&ebx, (char *)&edx, (char *)&ecx);

        printf("cpu information:\n");

        cpuid(1);
        printf(" family %ld model %ld stepping %ld efamily %ld emodel %ld\n",
                        b(eax, 8, 11), b(eax, 4, 7), b(eax, 0, 3), b(eax, 20, 27), b(eax, 16, 19));
        printf(" brand %ld cflush sz %ld*8 nproc %ld apicid %ld\n",
                        b(ebx, 0, 7), b(ebx, 8, 15), b(ebx, 16, 23), b(ebx, 24, 31));

        cpuid(0x80000006);
        printf("L1 cache size (per core): %ld KB\n", b(ecx, 16, 31));

        return(0);
}
Esempio n. 24
0
uint64_t get_microcode_version(void)
{
	uint64_t val;
	uint32_t eax, ebx, ecx, edx;

	msr_write(MSR_IA32_BIOS_SIGN_ID, 0U);
	cpuid(CPUID_FEATURES, &eax, &ebx, &ecx, &edx);
	val = msr_read(MSR_IA32_BIOS_SIGN_ID);

	return val;
}
Esempio n. 25
0
bool HvmIsImplemented(void)
{
	uint32_t eax, ebx, ecx, edx;
	cpuid(0, &eax, &ebx, &ecx, &edx);
	if (eax < 1) 
	{
		cprintf("HvmIsImplemented(): Extended CPUID functions not implemented\n");
		return FALSE;
	}
	if (!(ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)) 
	{
		cprintf("HvmIsImplemented(): Not an INTEL processor\n");
		return FALSE;
	}

	// intel cpu use fun_0x1 to test VMX.
	// CPUID.1:ECX.VMX[bit 5] = 1
	cpuid(0x1, &eax, &ebx, &ecx, &edx);
	return (bool) (CmIsBitSet (ecx, 5));
}
Esempio n. 26
0
void base_cpu_init(void)
{
	/* Detect the current processor.  */
	cpuid(&base_cpuid);

	/* Initialize the processor tables.  */
	base_trap_init();
	base_irq_init();
	base_gdt_init();
	base_tss_init();
}
Esempio n. 27
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static uint8_t
check_apic_avail (void)
{
    cpuid_ret_t cp;
    struct cpuid_feature_flags * flags;

    cpuid(CPUID_FEATURE_INFO, &cp);
    flags = (struct cpuid_feature_flags *)&cp.c;

    return flags->edx.apic;
}
Esempio n. 28
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static void setup_boot_cpu_data(void)
{
	int dummy, eax;

	/* get vendor info */
	cpuid(0, &boot_cpu_data.cpuid_level,
	      (int *)&boot_cpu_data.x86_vendor_id[0],
	      (int *)&boot_cpu_data.x86_vendor_id[8],
	      (int *)&boot_cpu_data.x86_vendor_id[4]);

	/* get cpu type
	 * &dummy, &boot_cpu_data.x86_capability); gets a warning
	 * because this address is bigger than 4GB, but we fortunately still
	 * have the V=R mapping.
	 */
	cpuid(1, &eax, &dummy, &dummy, &boot_cpu_data.x86_capability[0]);
	boot_cpu_data.x86 = (eax >> 8) & 0xf;
	boot_cpu_data.x86_model = (eax >> 4) & 0xf;
	boot_cpu_data.x86_mask = eax & 0xf;
}
Esempio n. 29
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 static void init() {
     // TODO: Chrome's not linking _sse* opts on iOS simulator builds.  Bug or feature?
 #if defined(SK_CPU_X86) && !defined(SK_BUILD_FOR_IOS)
     uint32_t abcd[] = {0,0,0,0};
     cpuid(abcd);
     if (abcd[2] & (1<< 9)) { Init_ssse3(); }
     if (abcd[2] & (1<<19)) { Init_sse41(); }
 #elif !defined(SK_ARM_HAS_NEON) && defined(SK_CPU_ARM32) && defined(SK_BUILD_FOR_ANDROID)
     if (android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_NEON) { Init_neon(); }
 #endif
 }
Esempio n. 30
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int main (int argc, char **argv)
{
	int eax,ebx,ecx,edx;
	cpuid(0x1,eax,ebx,ecx,edx);
	fprintf(stdout,"%s", (edx>>25)&1?"SSE ":"");
	fprintf(stdout,"%s", (edx>>26)&1?"SSE2 ":"");
	fprintf(stdout,"%s", (ecx)&1?"SSE3 ":"");
	fprintf(stdout,"%s", (ecx>>19)&1?"SSE4.1 ":"");
	fprintf(stdout,"%s", (ecx>>20)&1?"SSE4.2 ":"");
	fprintf(stdout,"\n");
}