/* this function checks the cache to see if the current state is cached,
if it is then it copies the cached data to the user region where code is
executed from, if its not cached then it gets decrypted to the current
cache position using the functions in s24_fd1094.c */
static void s24_fd1094_setstate_and_decrypt(running_machine *machine, int state)
{
int i;
UINT32 addr;
switch (state & 0x300)
{
case 0x000:
case FD1094_STATE_RESET:
fd1094_selected_state = state & 0xff;
break;
}
fd1094_state = state;
cpu_set_reg(cputag_get_cpu(machine, "sub"), M68K_PREF_ADDR, 0x0010); // force a flush of the prefetch cache
/* set the s24_fd1094 state ready to decrypt.. */
state = fd1094_set_state(s24_fd1094_key,state) & 0xff;
/* first check the cache, if its cached we don't need to decrypt it, just copy */
for (i = 0; i < S16_NUMCACHE; i++)
{
if (fd1094_cached_states[i] == state)
{
/* copy cached state */
s24_fd1094_userregion = s24_fd1094_cacheregion[i];
memory_set_decrypted_region(cputag_get_address_space(machine, "sub", ADDRESS_SPACE_PROGRAM), 0, s24_fd1094_cpuregionsize - 1, s24_fd1094_userregion);
m68k_set_encrypted_opcode_range(cputag_get_cpu(machine, "sub"), 0, s24_fd1094_cpuregionsize);
return;
}
}
// mame_printf_debug("new state %04x\n",state);
/* mark it as cached (because it will be once we decrypt it) */
fd1094_cached_states[fd1094_current_cacheposition] = state;
for (addr = 0; addr < s24_fd1094_cpuregionsize / 2; addr++)
{
UINT16 dat;
dat = fd1094_decode(addr, s24_fd1094_cpuregion[addr], s24_fd1094_key, 0);
s24_fd1094_cacheregion[fd1094_current_cacheposition][addr] = dat;
}
/* copy newly decrypted data to user region */
s24_fd1094_userregion = s24_fd1094_cacheregion[fd1094_current_cacheposition];
memory_set_decrypted_region(cputag_get_address_space(machine, "sub", ADDRESS_SPACE_PROGRAM), 0, s24_fd1094_cpuregionsize - 1, s24_fd1094_userregion);
m68k_set_encrypted_opcode_range(cputag_get_cpu(machine, "sub"), 0, s24_fd1094_cpuregionsize);
fd1094_current_cacheposition++;
if (fd1094_current_cacheposition >= S16_NUMCACHE)
{
mame_printf_debug("out of cache, performance may suffer, incrase S16_NUMCACHE!\n");
fd1094_current_cacheposition = 0;
}
}
MACHINE_DRIVER_END
/*************************************
*
* Driver Initialisation
*
*************************************/
static DRIVER_INIT( micro3d )
{
i8051_set_serial_tx_callback(cputag_get_cpu(machine, "audiocpu"), data_from_i8031);
i8051_set_serial_rx_callback(cputag_get_cpu(machine, "audiocpu"), data_to_i8031);
duart68681 = devtag_get_device( machine, "duart68681" );
}
void dc_update_interrupt_status(running_machine *machine)
{
int level;
if (dc_sysctrl_regs[SB_ISTERR])
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_ERROR;
}
else
{
dc_sysctrl_regs[SB_ISTNRM] &= ~IST_ERROR;
}
if (dc_sysctrl_regs[SB_ISTEXT])
{
dc_sysctrl_regs[SB_ISTNRM] |= IST_G1G2EXTSTAT;
}
else
{
dc_sysctrl_regs[SB_ISTNRM] &= ~IST_G1G2EXTSTAT;
}
level=dc_compute_interrupt_level(machine);
sh4_set_irln_input(cputag_get_cpu(machine, "maincpu"), 15-level);
}
static READ16_HANDLER( main_irqiack_r )
{
//fprintf(stderr, "M0: irq iack\n");
cpu_set_input_line(cputag_get_cpu(space->machine, "maincpu"), M68K_IRQ_1, CLEAR_LINE);
//cpu_set_input_line(cputag_get_cpu(space->machine, "maincpu"), INPUT_LINE_RESET, CLEAR_LINE);
return 0;
}
static WRITE8_HANDLER( pacland_irq_2_ctrl_w )
{
int bit = !BIT(offset, 13);
cpu_interrupt_enable(cputag_get_cpu(space->machine, "mcu"), bit);
if (!bit)
cputag_set_input_line(space->machine, "mcu", 0, CLEAR_LINE);
}
static MACHINE_START(quakeat)
{
cpu_set_irq_callback(cputag_get_cpu(machine, "maincpu"), irq_callback);
quakeat_devices.pic8259_1 = devtag_get_device( machine, "pic8259_1" );
quakeat_devices.pic8259_2 = devtag_get_device( machine, "pic8259_2" );
}
static WRITE8_HANDLER( irq1_ack_w )
{
int bit = data & 1;
cpu_interrupt_enable(cputag_get_cpu(space->machine, "sub"), bit);
if (!bit)
cputag_set_input_line(space->machine, "sub", 0, CLEAR_LINE);
}
void asic65_config(running_machine *machine, int asictype)
{
memset(&asic65, 0, sizeof(asic65));
asic65.type = asictype;
asic65.yorigin = 0x1800;
if (asic65.type == ASIC65_ROMBASED)
asic65.cpu = cputag_get_cpu(machine, "asic65");
}
static TIMER_CALLBACK( flyball_joystick_callback )
{
int potsense = param;
if (potsense & ~flyball_potmask)
generic_pulse_irq_line(cputag_get_cpu(machine, "maincpu"), 0);
flyball_potsense |= potsense;
}
static TIMER_CALLBACK( delayed_sound_w )
{
main_to_sound_data = param;
main_to_sound_ready = 1;
cpu_triggerint(cputag_get_cpu(machine, "audiocpu"));
/* use a timer to make long transfers faster */
timer_set(machine, ATTOTIME_IN_USEC(50), NULL, 0, 0);
}
static MACHINE_RESET( crimfght )
{
UINT8 *RAM = memory_region(machine, "maincpu");
konami_configure_set_lines(cputag_get_cpu(machine, "maincpu"), crimfght_banking);
/* init the default bank */
memory_set_bankptr(machine, 2, &RAM[0x10000] );
}
static void update_interrupts(running_machine *machine)
{
cputag_set_input_line(machine, "maincpu", 4, atarigen_video_int_state ? ASSERT_LINE : CLEAR_LINE);
if (cputag_get_cpu(machine, "extra") != NULL)
cputag_set_input_line(machine, "extra", 4, atarigen_video_int_state ? ASSERT_LINE : CLEAR_LINE);
cputag_set_input_line(machine, "maincpu", 6, atarigen_sound_int_state ? ASSERT_LINE : CLEAR_LINE);
}
static READ8_HANDLER( mcu_tnzs_r )
{
UINT8 data;
data = upi41_master_r(cputag_get_cpu(space->machine, "mcu"), offset & 1);
cpu_yield(space->cpu);
// logerror("PC %04x: read %02x from mcu $c00%01x\n", cpu_get_previouspc(space->cpu), data, offset);
return data;
}
static MACHINE_RESET( flyball )
{
int i;
/* address bits 0 through 8 are inverted */
UINT8* ROM = memory_region(machine, "maincpu") + 0x2000;
for (i = 0; i < 0x1000; i++)
rombase[i] = ROM[i ^ 0x1ff];
device_reset(cputag_get_cpu(machine, "maincpu"));
timer_set(machine, video_screen_get_time_until_pos(machine->primary_screen, 0, 0), NULL, 0, flyball_quarter_callback);
}
void devcb_resolve_read8(devcb_resolved_read8 *resolved, const devcb_read8 *config, const device_config *device)
{
/* reset the resolved structure */
memset(resolved, 0, sizeof(*resolved));
/* input port handlers */
if (config->type == DEVCB_TYPE_INPUT)
{
resolved->target = input_port_by_tag(device->machine->portconfig, config->tag);
if (resolved->target == NULL)
fatalerror("devcb_resolve_read8: unable to find input port '%s' (requested by %s '%s')", config->tag, device_get_name(device), device->tag);
resolved->read = trampoline_read_port_to_read8;
}
/* address space handlers */
else if (config->type >= DEVCB_TYPE_MEMORY(ADDRESS_SPACE_PROGRAM) && config->type < DEVCB_TYPE_MEMORY(ADDRESS_SPACES) && config->readspace != NULL)
{
FPTR space = (FPTR)config->type - (FPTR)DEVCB_TYPE_MEMORY(ADDRESS_SPACE_PROGRAM);
const device_config *cpu = cputag_get_cpu(device->machine, config->tag);
if (cpu == NULL)
fatalerror("devcb_resolve_read8: unable to find CPU '%s' (requested by %s '%s')", config->tag, device_get_name(device), device->tag);
resolved->target = memory_find_address_space(cpu, space);
if (resolved->target == NULL)
fatalerror("devcb_resolve_read8: unable to find CPU '%s' %s space (requested by %s '%s')", config->tag, address_space_names[space], device_get_name(device), device->tag);
resolved->read = (read8_device_func)config->readspace;
}
/* device handlers */
else if ((config->type == DEVCB_TYPE_DEVICE || config->type == DEVCB_TYPE_SELF) && (config->readline != NULL || config->readdevice != NULL))
{
resolved->target = (config->type == DEVCB_TYPE_SELF) ? device : devtag_get_device(device->machine, config->tag);
if (resolved->target == NULL)
fatalerror("devcb_resolve_read8: unable to find device '%s' (requested by %s '%s')", config->tag, device_get_name(device), device->tag);
/* read8 to read8 is direct */
if (config->readdevice != NULL)
resolved->read = config->readdevice;
/* read8 to read_line goes through a trampoline */
else
{
resolved->realtarget = resolved->target;
resolved->real.readline = config->readline;
resolved->target = resolved;
resolved->read = trampoline_read_line_to_read8;
}
}
}
static INTERRUPT_GEN( chl_interrupt )
{
int vector = video_screen_get_vblank(device->machine->primary_screen) ? 0xdf : 0xcf; /* 4 irqs per frame: 3 times 0xcf, 1 time 0xdf */
// video_screen_update_partial(device->machine->primary_screen, video_screen_get_vpos(device->machine->primary_screen));
cpu_set_input_line_and_vector(device, 0, HOLD_LINE, vector);
/* it seems the V8 == Vblank and it is connected to the INT on the 68705 */
//so we should cause an INT on the MCU cpu here, as well.
//but only once per frame !
if (vector == 0xdf) /* only on vblank */
generic_pulse_irq_line(cputag_get_cpu(device->machine, "mcu"), 0);
}
static TIMER_CALLBACK( interrupt_callback )
{
int scanline = param;
update_plunger(machine);
generic_pulse_irq_line(cputag_get_cpu(machine, "maincpu"), 0);
scanline = scanline + 32;
if (scanline >= 262)
scanline = 16;
timer_set(machine, video_screen_get_time_until_pos(machine->primary_screen, scanline, 0), NULL, scanline, interrupt_callback);
}
static WRITE16_HANDLER( eprom_latch_w )
{
if (ACCESSING_BITS_0_7 && (cputag_get_cpu(space->machine, "extra") != NULL))
{
/* bit 0: reset extra CPU */
if (data & 1)
cputag_set_input_line(space->machine, "extra", INPUT_LINE_RESET, CLEAR_LINE);
else
cputag_set_input_line(space->machine, "extra", INPUT_LINE_RESET, ASSERT_LINE);
/* bits 1-4: screen intensity */
eprom_screen_intensity = (data & 0x1e) >> 1;
/* bit 5: video disable */
eprom_video_disable = (data & 0x20);
}
}
ROM_END
/*-------------------------------------------------
device start callback
-------------------------------------------------*/
static DEVICE_START( namco_50xx )
{
namco_50xx_state *state = get_safe_token(device);
astring *tempstring = astring_alloc();
/* find our CPU */
state->cpu = cputag_get_cpu(device->machine, device_build_tag(tempstring, device, "mcu"));
assert(state->cpu != NULL);
astring_free(tempstring);
}
static WRITE8_DEVICE_HANDLER( friskyt_portB_w )
{
//logerror("PC %04x: 8910 port B = %02x\n",cpu_get_pc(space->cpu),data);
/* bit 0 is IRQ enable */
cpu_interrupt_enable(cputag_get_cpu(device->machine, "maincpu"), data & 1);
/* bit 1 flips screen */
/* bit 2 resets the microcontroller */
if (((portb & 4) == 0) && (data & 4))
{
/* reset and start the protection mcu */
cputag_set_input_line(device->machine, "mcu", INPUT_LINE_RESET, PULSE_LINE);
cputag_set_input_line(device->machine, "mcu", INPUT_LINE_HALT, CLEAR_LINE);
}
/* other bits unknown */
portb = data;
}
static TIMER_CALLBACK( scanline_update )
{
int scanline = param;
/* WARNING: the timing of this is not perfectly accurate; it should fire on
32V (i.e., on scanlines 32, 96, 160, and 224). However, due to the interrupt
structure, it cannot fire at the same time as VBLANK. I have not solved this
mystery yet */
/* INT 1 is on 32V */
atarigen_scanline_int_gen(cputag_get_cpu(machine, "maincpu"));
/* advance to the next interrupt */
scanline += 64;
if (scanline > 192)
scanline = 0;
/* set a timer for it */
timer_adjust_oneshot(scanline_timer, video_screen_get_time_until_pos(machine->primary_screen, scanline, 0), scanline);
}
static MACHINE_RESET( mexico86 )
{
/*TODO: check the PCB and see how the halt / reset lines are connected. */
if (cputag_get_cpu(machine, "sub") != NULL)
cputag_set_input_line(machine, "sub", INPUT_LINE_RESET, (input_port_read(machine, "DSW1") & 0x80) ? ASSERT_LINE : CLEAR_LINE);
}
static void scanline_update(const device_config *screen, int scanline)
{
/* generate 32V signals */
if ((scanline & 32) == 0 && !(input_port_read(screen->machine, "P1") & 0x800))
atarigen_scanline_int_gen(cputag_get_cpu(screen->machine, "maincpu"));
}
static READ16_HANDLER( tms_host_r )
{
return tms34010_host_r(cputag_get_cpu(space->machine, "vgb"), offset);
}
static WRITE16_HANDLER( wiggle_i860p1_pins_w )
{
wiggle_i860_common(cputag_get_cpu(space->machine, "vid_1"), data);
}
static WRITE16_HANDLER( tms_host_w )
{
tms34010_host_w(cputag_get_cpu(space->machine, "vgb"), offset, data);
}
static READ16_HANDLER( exterm_host_data_r )
{
return tms34010_host_r(cputag_get_cpu(space->machine, "slave"), offset / TOWORD(0x00100000));
}
static WRITE16_HANDLER( exterm_host_data_w )
{
tms34010_host_w(cputag_get_cpu(space->machine, "slave"), offset / TOWORD(0x00100000), data);
}
static WRITE8_HANDLER( mcu_tnzs_w )
{
// logerror("PC %04x: write %02x to mcu $c00%01x\n", cpu_get_previouspc(space->cpu), data, offset);
upi41_master_w(cputag_get_cpu(space->machine, "mcu"), offset & 1, data);
}
static MACHINE_RESET( aztarac )
{
cpu_set_irq_callback(cputag_get_cpu(machine, "maincpu"), aztarac_irq_callback);
}
