Esempi in C++ (Cpp) per cti_enable_access

Esempio n. 1

File: coresight-v7.c Progetto: Fnoeoe/android_kernel_samsung_grandprimevelte

static void coresight_cti_restore(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	writel_relaxed(p_cti_info->cti_en_in1, CTI_REG(CTI_EN_IN1_OFFSET));
	writel_relaxed(p_cti_info->cti_en_out6, CTI_REG(CTI_EN_OUT6_OFFSET));
	writel_relaxed(p_cti_info->cti_ctrl, CTI_REG(CTI_CTRL_OFFSET));
}

Esempio n. 2

File: coresight-v7.c Progetto: Fnoeoe/android_kernel_samsung_grandprimevelte

static void coresight_cti_save(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	p_cti_info->cti_ctrl = readl_relaxed(CTI_REG(CTI_CTRL_OFFSET));
	p_cti_info->cti_en_in1 = readl_relaxed(CTI_REG(CTI_EN_IN1_OFFSET));
	p_cti_info->cti_en_out6 = readl_relaxed(CTI_REG(CTI_EN_OUT6_OFFSET));
}

Esempio n. 3

File: coresight-v7.c Progetto: 12019/android_kernel_samsung_lt02wifi

static void coresight_cti_save(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	p_cti_info->cti_ctrl = readl_relaxed(CTI_REG(0x0));
	p_cti_info->cti_en_in1 = readl_relaxed(CTI_REG(0x24));
	p_cti_info->cti_en_out6 = readl_relaxed(CTI_REG(0xb8));
}

Esempio n. 4

File: coresight-v7.c Progetto: 12019/android_kernel_samsung_lt02wifi

static void coresight_cti_restore(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	writel_relaxed(p_cti_info->cti_ctrl, CTI_REG(0x0));
	writel_relaxed(p_cti_info->cti_en_in1, CTI_REG(0x24));
	writel_relaxed(p_cti_info->cti_en_out6, CTI_REG(0xB8));

	dsb();
	isb();
}

Esempio n. 5

File: coresight-v8.c Progetto: acorn-marvell/brillo_pxa_kernel

void arch_restart_cpu(u32 cpu)
{
	u32 timeout, val;
	void __iomem *p_dbg_base = DBG_BASE(cpu);
	void __iomem *p_cti_base = CTI_BASE(cpu);

	/* Disable Halt Debug Mode */
	val = readl(p_dbg_base + EDSCR);
	val &= ~(0x1 << 14);
	writel(val, p_dbg_base + EDSCR);

	/* Enable CTI access */
	cti_enable_access(cpu);

	/* Enable CTI */
	writel(0x1, p_cti_base + CTI_CTRL);

	/* ACK the outut event */
	writel(0x1, p_cti_base + CTI_INTACK);

	/* Set output channel1 */
	val = readl(p_cti_base + CTI_OUT1EN) | 0x2;
	writel(val, p_cti_base + CTI_OUT1EN);

	/* Trigger pulse event */
	writel(0x2, p_cti_base + CTI_APP_PULSE);

	/* Wait the cpu become running */
	timeout = 10000;
	do {
		val = readl(p_dbg_base + EDPRSR);
		if (!(val & (0x1 << 4)))
			break;
	} while (--timeout);

	if (!timeout)
		pr_emerg("Cannot restart cpu%d\n", cpu);
}

Esempio n. 6

File: coresight-v8.c Progetto: acorn-marvell/brillo_pxa_kernel

int arch_halt_cpu(u32 cpu)
{
	u32 timeout, val;
	void __iomem *p_dbg_base = DBG_BASE(cpu);
	void __iomem *p_cti_base = CTI_BASE(cpu);
	/* Enable Halt Debug mode */
	val = readl(p_dbg_base + EDSCR);
	val |= (0x1 << 14);
	writel(val, p_dbg_base + EDSCR);

	/* Enable CTI access */
	cti_enable_access(cpu);

	/* Enable CTI */
	writel(0x1, p_cti_base + CTI_CTRL);

	/* Set output channel0 */
	val = readl(p_cti_base + CTI_OUT0EN) | 0x1;
	writel(val, p_cti_base + CTI_OUT0EN);

	/* Trigger pulse event */
	writel(0x1, p_cti_base + CTI_APP_PULSE);

	/* Wait the cpu halted */
	timeout = 10000;
	do {
		val = readl(p_dbg_base + EDPRSR);
		if (val & (0x1 << 4))
			break;
	} while (--timeout);

	if (!timeout)
		return -1;

	return 0;
}