static void devV792_AO_SET_PEDESTAL(ST_execParam *pParam)
{
ST_STD_device *pSTDdev = pParam->pSTDdev;
struct dbCommon *precord = pParam->precord;
/* ST_MASTER *pAdminCfg = pSTDdev->pST_parentAdmin; */
ST_V792 *pV792 = (ST_V792 *)pSTDdev->pUser;
UINT16 reg_value, cur_value;
if( (UINT16)pParam->setValue > 255 )
{
epicsPrintf("ERROR! %s: Over the max value (%d)\n", pSTDdev->taskName, (UINT16)pParam->setValue );
return;
}
cur_value = (UINT16)pParam->setValue;
cvt_read_reg( &pV792->board_data.m_common_data, CVT_V792_IPED_INDEX, ®_value);
epicsPrintf("%s: Current Pedestal (%d)\n", pSTDdev->taskName, reg_value);
if ( !cvt_V792_set_pedestal( &pV792->board_data, cur_value)) {
notify_error(1,"%s: pedestal(%d)", pSTDdev->taskName, cur_value);
return;
}
cvt_read_reg( &pV792->board_data.m_common_data, CVT_V792_IPED_INDEX, ®_value);
pV792->Pedestal = reg_value;
epicsPrintf("New Pedestal:%d %s %s (%s)\n", pV792->Pedestal,
pSTDdev->taskName, precord->name, epicsThreadGetNameSelf());
}
BOOL cvt_V1190_read_from_micro( cvt_V1190_data* p_data, UINT16 ope_code, UINT16* p_params, int num_params)
{
UINT16 micro_hnd= 0;
// wait for micro register write ok
do
{
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_HND_INDEX, µ_hnd))
{
return FALSE;
}
} while( !(micro_hnd& CVT_V1190_MICRO_HND_WRITEOK_MSK));
// write opcode to micro register
if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MICRO_INDEX, &ope_code))
{
return FALSE;
}
// read ope code
while( num_params--)
{
// wait for micro register read ok
do
{
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_HND_INDEX, µ_hnd))
{
return FALSE;
}
} while( !(micro_hnd& CVT_V1190_MICRO_HND_READOK_MSK));
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_INDEX, p_params++))
{
return FALSE;
}
}
return TRUE;
}
BOOL cvt_V1190_get_event_stored( cvt_V1190_data* p_data, UINT16* p_counter)
{
UINT16 reg_value;
*p_counter= 0;
// Event stored
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_EVENT_STORED_INDEX, ®_value))
{
TRACE( "V1190 CVT_V1190_EVENT_STORED read failed !\n");
return FALSE;
}
*p_counter= reg_value;
return TRUE;
}
BOOL cvt_V1190_get_event_counter( cvt_V1190_data* p_data, UINT32* p_counter)
{
UINT32 reg_value;
*p_counter= 0;
// Event Counter
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_EVENT_COUNTER_INDEX, ®_value))
{
TRACE( "V1190 CVT_V1190_EVENT_COUNTER read failed !\n");
return FALSE;
}
*p_counter= reg_value;
return TRUE;
}
BOOL cvt_V1190_get_status( cvt_V1190_data* p_data, BOOL *p_is_data_ready, BOOL *p_is_term_on, BOOL *p_is_buffer_full, BOOL *p_is_buffer_almost_full, CVT_V1190_STATUS_RES* p_resolution, UINT8* p_error_bitmask)
{
UINT16 reg_value= 0;
//
// read status register
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_STATUS_INDEX, ®_value))
{
TRACE( "V1190 CVT_V1190_STATUS read failed !\n");
return FALSE;
}
*p_is_data_ready= ( reg_value& CVT_V1190_STS_DREADY_MSK)? TRUE: FALSE;
*p_is_term_on= ( reg_value& CVT_V1190_STS_TERM_ON_MSK)? TRUE: FALSE;
*p_is_buffer_full= ( reg_value& CVT_V1190_STS_FULL_MSK)? TRUE: FALSE;
*p_is_buffer_almost_full= ( reg_value& CVT_V1190_STS_ALMOST_FULL_MSK)? TRUE: FALSE;
*p_resolution= CVT_V1190_GET_STATUS_RES( reg_value);
*p_error_bitmask= CVT_V1190_GET_STATUS_ERROR( reg_value);
return TRUE;
}
BOOL cvt_V1190_get_system_info( cvt_V1190_data* p_data, UINT16 *p_firmware_rev, UINT32 *p_tdc_id_buff, UINT16 *p_micro_firmware_rev, UINT16 *p_serial_number)
{
UINT16 reg_value= 0;
UINT32 reg_value32= 0;
int num_tdc= 0;
switch( p_data->m_type)
{
case CVT_V1190_TYPE_A: /*!< The board is V1190A */
num_tdc= CVT_V1190_NUM_TDC_A;
break;
case CVT_V1190_TYPE_B: /*!< The board is V1190B */
num_tdc= CVT_V1190_NUM_TDC_B;
break;
case CVT_V1290_TYPE_A: /*!< The board is V1290A */
num_tdc= CVT_V1290_NUM_TDC_A;
break;
case CVT_V1290_TYPE_N: /*!< The board is V1290N */
num_tdc= CVT_V1290_NUM_TDC_N;
break;
default:
TRACE1( "cvt_V1190_get_system_info: bad board type: %d\n", p_data->m_type);
return FALSE;
}
//
// Firmware revision register
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_FW_REV_INDEX, ®_value))
{
TRACE( "V1190 CVT_V1190_FW_REV read failed !\n");
return FALSE;
}
*p_firmware_rev= (( reg_value& 0x00f0)<< 4)|( reg_value& 0x000f);
//
// TDC IDs
while( num_tdc--)
{
if( !cvt_V1190_read_from_micro( p_data, CVT_V1190_READ_TDC_ID_OPCODE+ num_tdc, (UINT16*)®_value32, 2))
{
TRACE( "V1190 CVT_V1190_READ_TDC_ID_OPCODE opcode read failed !\n");
return FALSE;
}
p_tdc_id_buff[ num_tdc]= reg_value32;
// (( reg_value& 0x00f0)<< 4)|( reg_value& 0x000f);
}
//
// Microcontroller firmware revision
if( !cvt_V1190_read_from_micro( p_data, CVT_V1190_READ_MICRO_REV_OPCODE, ®_value, 1))
{
TRACE( "V1190 CVT_V1190_READ_MICRO_REV_OPCODE opcode read failed !\n");
return FALSE;
}
*p_micro_firmware_rev= (( reg_value& 0x00f0)<< 4)|( reg_value& 0x000f);
//
// Serial number
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_ROM_SERIAL_0_INDEX, ®_value))
{
TRACE( "V1190 CVT_V1190_ROM_SERIAL_LSB read failed !\n");
return FALSE;
}
*p_serial_number= reg_value& 0x00ff;
if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_ROM_SERIAL_1_INDEX, ®_value))
{
TRACE( "V1190 CVT_V1190_ROM_SERIAL_MSB read failed !\n");
return FALSE;
}
*p_serial_number|= (reg_value& 0x00ff)<< 8;
return TRUE;
}