//=========================================================================== // Initialize CAN driver //=========================================================================== static void can_init(can_channel *chan) { can_cbuf_t *cbuf; if (chan->init) { return; } cbuf = &chan->in_cbuf; cbuf->waiting = false; cbuf->abort = false; #ifdef CYGOPT_IO_CAN_SUPPORT_NONBLOCKING cbuf->blocking = true; #endif cyg_drv_mutex_init(&cbuf->lock); cyg_drv_cond_init(&cbuf->wait, &cbuf->lock); cbuf = &chan->out_cbuf; cbuf->waiting = false; cbuf->abort = false; #ifdef CYGOPT_IO_CAN_SUPPORT_NONBLOCKING cbuf->blocking = true; #endif cyg_drv_mutex_init(&cbuf->lock); cyg_drv_cond_init(&cbuf->wait, &cbuf->lock); chan->init = true; }
static cyg_bool disk_init(struct cyg_devtab_entry *tab) { disk_channel *chan = (disk_channel *) tab->priv; cyg_disk_info_t *info = chan->info; int i; //diag_printf("file test:disk_init\n"); if (!chan->init) { disk_controller *controller = chan->controller; if( !controller->init ) { cyg_drv_mutex_init( &controller->lock ); cyg_drv_cond_init( &controller->queue, &controller->lock ); cyg_drv_cond_init( &controller->async, &controller->lock ); controller->init = true; } info->connected = false; // clear partition data for (i = 0; i < info->partitions_num; i++) info->partitions[i].type = 0x00; //info->partitions.type = 0x00; chan->init = true; } //diag_printf("file test:disk_init end\n"); return true; }
//========================================================================== // Initialize driver & hardware state //========================================================================== void cyg_lpc2xxx_i2c_init(struct cyg_i2c_bus *bus) { cyg_lpc2xxx_i2c_extra* extra = (cyg_lpc2xxx_i2c_extra*)bus->i2c_extra; cyg_uint16 duty_cycle; cyg_drv_mutex_init(&extra->i2c_lock); cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock); cyg_drv_interrupt_create(I2C_ISRVEC(extra), I2C_ISRPRI(extra), (cyg_addrword_t) extra, &lpc2xxx_i2c_isr, &lpc2xxx_i2c_dsr, &(extra->i2c_interrupt_handle), &(extra->i2c_interrupt_data)); cyg_drv_interrupt_attach(extra->i2c_interrupt_handle); CLR_CON(extra, CON_EN | CON_STA | CON_SI | CON_AA); HAL_WRITE_UINT8(I2C_ADR(extra), 0); // // Setup I2C bus frequency // duty_cycle = (I2C_CLK(extra) / I2C_BUS_FREQ(extra)) / 2; HAL_WRITE_UINT16(I2C_SCLL(extra), duty_cycle); HAL_WRITE_UINT16(I2C_SCLH(extra), duty_cycle); SET_CON(extra, CON_EN); }
void hasp_mpc5xxx_i2c_init() { initReset(); // initialise the reset pin resetHigh(); cyg_drv_mutex_init(&i2c_lock); cyg_drv_cond_init(&i2c_wait, &i2c_lock); cyg_drv_interrupt_create(i2c_intr_vector, 0, (cyg_addrword_t) 0, &mpc5xxx_i2c_isr, &mpc5xxx_i2c_dsr, &(i2c_interrupt_handle), &(i2c_interrupt_data)); cyg_drv_interrupt_attach(i2c_interrupt_handle); HAL_WRITE_UINT32(I2C_0_FDR_REG, 0x89000000); // Set clock to 100MHz / 352 HAL_WRITE_UINT32(I2C_0_ADDRESS_REG, 0x00000000); // Set MPC5xxx slave address, not useful to us HAL_WRITE_UINT32(I2C_0_CONTROL_REG, I2C_ENABLE); // Enable the I2C device but do not start any transfers and leave interrupts disabled. HAL_WRITE_UINT32(I2C_0_STATUS_REG, 0x00000000); // Clear any pending conditions including interrupts. HAL_INTERRUPT_UNMASK(i2c_intr_vector); // Interrupts can now be safely unmasked i2c_flag = 0; resetLow(); }
void cyg_spi_at91_bus_init(void) { // Create and attach SPI interrupt object cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_SPI, 4, (cyg_addrword_t)&cyg_spi_at91_bus, spi_at91_ISR, spi_at91_DSR, &cyg_spi_at91_bus.spi_interrupt_handle, &cyg_spi_at91_bus.spi_interrupt); cyg_drv_interrupt_attach(cyg_spi_at91_bus.spi_interrupt_handle); // Init transfer mutex and condition cyg_drv_mutex_init(&cyg_spi_at91_bus.transfer_mx); cyg_drv_cond_init(&cyg_spi_at91_bus.transfer_cond, &cyg_spi_at91_bus.transfer_mx); // Init flags cyg_spi_at91_bus.transfer_end = true; cyg_spi_at91_bus.cs_up = false; // Soft reset the SPI controller HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SWRST); // Configure SPI pins // NOTE: here we let the SPI controller control // the data in, out and clock signals, but // we need to handle the chip selects manually // in order to achieve better chip select control // inbetween transactions. // Put SPI MISO, MOIS and SPCK pins into peripheral mode HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PDR, AT91_PIO_PSR_SPCK | AT91_PIO_PSR_MISO | AT91_PIO_PSR_MOIS); // Put SPI chip select pins in IO output mode HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_SODR, AT91_SPI_PIO_NPCS(0x0F)); HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PER, AT91_SPI_PIO_NPCS(0x0F)); HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_OER, AT91_SPI_PIO_NPCS(0x0F)); // Call upper layer bus init CYG_SPI_BUS_COMMON_INIT(&cyg_spi_at91_bus.spi_bus); }
Cyg_ErrNo usbs_devtab_cwrite(cyg_io_handle_t handle, const void* buf, cyg_uint32* size) { usbs_callback_data wait; cyg_devtab_entry_t* devtab_entry; usbs_tx_endpoint* endpoint; int result = ENOERR; CYG_REPORT_FUNCTION(); wait.completed = 0; cyg_drv_mutex_init(&wait.lock); cyg_drv_cond_init(&wait.signal, &wait.lock); devtab_entry = (cyg_devtab_entry_t*) handle; CYG_CHECK_DATA_PTR( devtab_entry, "A valid endpoint must be supplied"); endpoint = (usbs_tx_endpoint*) devtab_entry->priv; CYG_CHECK_DATA_PTR( endpoint, "The handle must correspond to a USB endpoint"); CYG_CHECK_FUNC_PTR( endpoint->start_tx_fn, "The endpoint must have a start_tx function"); endpoint->buffer = (unsigned char*) buf; endpoint->buffer_size = (int) *size; endpoint->complete_fn = &usbs_devtab_callback; endpoint->complete_data = (void*) &wait; (*endpoint->start_tx_fn)(endpoint); cyg_drv_mutex_lock(&wait.lock); cyg_drv_dsr_lock(); while (!wait.completed) { cyg_drv_cond_wait(&wait.signal); } cyg_drv_dsr_unlock(); cyg_drv_mutex_unlock(&wait.lock); if (wait.result < 0) { result = wait.result; } else { *size = wait.result; } cyg_drv_cond_destroy(&wait.signal); cyg_drv_mutex_destroy(&wait.lock); CYG_REPORT_RETURN(); return result; }
static void spi_at91_init_bus(cyg_spi_at91_bus_t * spi_bus) { cyg_uint32 ctr; // Create and attach SPI interrupt object cyg_drv_interrupt_create(spi_bus->interrupt_number, 4, (cyg_addrword_t)spi_bus, spi_at91_ISR, spi_at91_DSR, &spi_bus->spi_interrupt_handle, &spi_bus->spi_interrupt); cyg_drv_interrupt_attach(spi_bus->spi_interrupt_handle); // Init transfer mutex and condition cyg_drv_mutex_init(&spi_bus->transfer_mx); cyg_drv_cond_init(&spi_bus->transfer_cond, &spi_bus->transfer_mx); // Init flags spi_bus->transfer_end = true; spi_bus->cs_up = false; // Soft reset the SPI controller HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SWRST); // Configure SPI pins // Put SPI chip select pins in IO output mode for(ctr = 0;ctr<4;ctr++) { if(spi_bus->cs_en[ctr]) { HAL_ARM_AT91_GPIO_CFG_DIRECTION(spi_bus->cs_gpio[ctr],AT91_PIN_OUT); HAL_ARM_AT91_GPIO_SET(spi_bus->cs_gpio[ctr]); } } // Call upper layer bus init CYG_SPI_BUS_COMMON_INIT(&spi_bus->spi_bus); }
static void serial_init(serial_channel *chan) { if (chan->init) return; if (chan->out_cbuf.len != 0) { #ifdef CYGDBG_IO_INIT diag_printf("Set output buffer - buf: %x len: %d\n", chan->out_cbuf.data, chan->out_cbuf.len); #endif chan->out_cbuf.waiting = false; chan->out_cbuf.abort = false; #ifdef CYGOPT_IO_SERIAL_SUPPORT_NONBLOCKING chan->out_cbuf.blocking = true; #endif chan->out_cbuf.pending = 0; cyg_drv_mutex_init(&chan->out_cbuf.lock); cyg_drv_cond_init(&chan->out_cbuf.wait, &chan->out_cbuf.lock); chan->out_cbuf.low_water = chan->out_cbuf.len / 4; #ifdef CYGPKG_IO_SERIAL_SELECT_SUPPORT cyg_selinit( &chan->out_cbuf.selinfo ); #endif } if (chan->in_cbuf.len != 0) { cbuf_t *cbuf = &chan->in_cbuf; #ifdef CYGDBG_IO_INIT diag_printf("Set input buffer - buf: %x len: %d\n", cbuf->data, cbuf->len); #endif cbuf->waiting = false; cbuf->abort = false; #ifdef CYGOPT_IO_SERIAL_SUPPORT_NONBLOCKING cbuf->blocking = true; #endif #ifdef CYGPKG_IO_SERIAL_SELECT_SUPPORT cyg_selinit( &cbuf->selinfo ); #endif #ifdef CYGPKG_IO_SERIAL_FLOW_CONTROL cbuf->low_water = (CYGNUM_IO_SERIAL_FLOW_CONTROL_LOW_WATER_PERCENT * cbuf->len) / 100; cbuf->high_water = (CYGNUM_IO_SERIAL_FLOW_CONTROL_HIGH_WATER_PERCENT * cbuf->len) / 100; # ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_SOFTWARE // But make sure it is at least 35 below buffer size, to allow // for 16 byte fifos, twice, plus some latency before s/w flow // control can kick in. This doesn't apply to h/w flow control // as it is near-instaneous if ( (cbuf->len - cbuf->high_water) < 35 ) cbuf->high_water = cbuf->len - 35; // and just in case... if ( cbuf->high_water <= 0 ) cbuf->high_water = 1; if ( cbuf->low_water > cbuf->high_water ) cbuf->low_water = cbuf->high_water; # endif #endif cyg_drv_mutex_init(&cbuf->lock); cyg_drv_cond_init(&cbuf->wait, &cbuf->lock); } #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS chan->status_callback = NULL; #endif #ifdef CYGDBG_USE_ASSERTS #if CYGINT_IO_SERIAL_BLOCK_TRANSFER chan->in_cbuf.block_mode_xfer_running = false; chan->out_cbuf.block_mode_xfer_running = false; #endif // CYGINT_IO_SERIAL_BLOCK_TRANSFER #endif // CYGDBG_USE_ASSERTS #ifdef CYGPKG_NET_BLUEZ_STACK //diag_printf("sizeof(serial_channel) = %d cbuf_t %d\n", sizeof(serial_channel), sizeof(cbuf_t)); //diag_printf("chan->in_cbuf.data=%x,in_cbuf.len=%x,chan->out_cbuf.data=%x\n",chan->in_cbuf.data,chan->in_cbuf.len,chan->out_cbuf.data); chan->receive = 0;//clyu chan->tty_ldisc = NULL; #endif chan->init = true; }
/** * * QSPI bus initialization function * * @param qspi_bus - Driver handle * * @return none * *****************************************************************************/ static void qspi_xc7z_init_bus(cyg_qspi_xc7z_bus_t * qspi_bus) { entry_debug(); volatile cyg_uint32 reg; // Create and attach SPI interrupt object cyg_drv_interrupt_create(qspi_bus->interrupt_number, 4, (cyg_addrword_t)qspi_bus, qspi_xc7z_ISR, qspi_xc7z_DSR, &qspi_bus->qspi_interrupt_handle, &qspi_bus->qspi_interrupt); cyg_drv_interrupt_attach(qspi_bus->qspi_interrupt_handle); cyg_drv_interrupt_mask(qspi_bus->interrupt_number); // Init transfer mutex and condition cyg_drv_mutex_init(&qspi_bus->transfer_mx); cyg_drv_cond_init(&qspi_bus->transfer_cond, &qspi_bus->transfer_mx); // Init flags qspi_bus->transfer_end = true; qspi_bus->cs_up = false; // Unlock SLCR regs HAL_WRITE_UINT32(XC7Z_SYS_CTRL_BASEADDR + XSLCR_UNLOCK_OFFSET, XSLCR_UNLOCK_KEY); // Enable clock to QSPI module HAL_READ_UINT32( XC7Z_SYS_CTRL_BASEADDR + XSLCRAPER_CLK_CTRL_OFFSET, reg); reg |= XSLCRAPER_CLK_CTRL_QSPI_EN; HAL_WRITE_UINT32(XC7Z_SYS_CTRL_BASEADDR + XSLCRAPER_CLK_CTRL_OFFSET, reg); // Lock SLCR regs HAL_WRITE_UINT32(XC7Z_SYS_CTRL_BASEADDR + XSLCR_LOCK_OFFSET, XSLCR_LOCK_KEY); // Soft reset the SPI controller HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_ER_OFFSET, 0x00); //TODO changed, originally was just setting a value without reading HAL_READ_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg); reg &= (1 << 17); // preserve the reserved bit which is described as "do not modify" reg |= (1 << 31); HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg); // Disable linear mode HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_LQSPI_CR_OFFSET, 0x00); // Clear status HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, 0x7F); // Clear the RX FIFO HAL_READ_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, reg); while (reg & XQSPIPS_IXR_RXNEMPTY_MASK) { HAL_READ_UINT32(qspi_bus->base + XQSPIPS_RXD_OFFSET, reg); HAL_READ_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, reg); } HAL_READ_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg); reg &= 0xFBFFFFFF; /* Set little endian mode of TX FIFO */ reg |= (XQSPIPS_CR_IFMODE_MASK | XQSPIPS_CR_MANSTRTEN_MASK | XQSPIPS_CR_SSFORCE_MASK | XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_DATA_SZ_MASK | XQSPIPS_CR_MSTREN_MASK); HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg); // Configure SPI pins // All pins was configured in HAL // Call upper layer bus init CYG_SPI_BUS_COMMON_INIT(&qspi_bus->qspi_bus); }
static void dspi_bus_setup(cyg_spi_freescale_dspi_bus_t* spi_bus_p) { cyghwr_devs_freescale_dspi_t* dspi_p = spi_bus_p->setup_p->dspi_p; cyghwr_hal_freescale_dma_set_t* dma_set_p; cyghwr_hal_freescale_edma_t* edma_p; cyg_uint32 dma_chan_i; // Get the clock frequency from HAL. spi_bus_p->clock_freq = CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK; DEBUG1_PRINTF("DSPI BUS %p: SysClk=%d\n", spi_bus_p, spi_bus_p->clock_freq); // Set up the pins. dspi_pin_setup(spi_bus_p->setup_p->spi_pin_list_p, spi_bus_p->setup_p->cs_pin_list_p, spi_bus_p->setup_p->cs_pin_num); // Set up default SPI configuration. dspi_p->mcr = spi_bus_p->setup_p->mcr_opt | FREESCALE_DSPI_MCR_MSTR_M | FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M | FREESCALE_DSPI_MCR_MDIS_M; // Enable DSPI controller. dspi_enable(dspi_p); if((dma_set_p=spi_bus_p->setup_p->dma_set_p)) { // Initialize DMA channels hal_freescale_edma_init_chanset(dma_set_p); #if DEBUG_SPI >= 1 hal_freescale_edma_diag(dma_set_p, 0xffff); cyghwr_devs_freescale_dspi_diag(spi_bus_p); #endif // Set up DMA transfer control descriptors edma_p = dma_set_p->edma_p; dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_TX_I].dma_chan_i; hal_freescale_edma_transfer_init(edma_p, dma_chan_i, spi_bus_p->tx_dma_tcd_ini_p); #if DEBUG_SPI >= 1 hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true); #endif dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_RX_I].dma_chan_i; hal_freescale_edma_transfer_init(edma_p, dma_chan_i, spi_bus_p->rx_dma_tcd_ini_p); #if DEBUG_SPI >= 1 hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true); #endif // Enable SPI DMA requests dspi_p->rser = FREESCALE_DSPI_RSER_TFFF_DIRS_M | FREESCALE_DSPI_RSER_RFDF_DIRS_M | FREESCALE_DSPI_RSER_TFFF_RE_M | FREESCALE_DSPI_RSER_RFDF_RE_M; } #if DEBUG_SPI >= 1 cyghwr_devs_freescale_dspi_diag(spi_bus_p); #endif // Initialise the synchronisation primitivies. cyg_drv_mutex_init (&spi_bus_p->transfer_mutex); cyg_drv_cond_init (&spi_bus_p->transfer_done, &spi_bus_p->transfer_mutex); // Hook up the ISR and DSR. cyg_drv_interrupt_create (spi_bus_p->setup_p->intr_num, spi_bus_p->setup_p->intr_prio, (cyg_addrword_t) spi_bus_p, dma_set_p ? dspi_dma_ISR : dspi_nodma_ISR, dspi_DSR, &spi_bus_p->intr_handle, &spi_bus_p->intr_data); cyg_drv_interrupt_attach (spi_bus_p->intr_handle); dspi_p->ctar[1] = dspi_calc_ctar(&aux_clocking, spi_bus_p->clock_freq); // Call upper layer bus init. CYG_SPI_BUS_COMMON_INIT(&spi_bus_p->spi_bus); }
/* * Initialize driver and hardware */ void zynq_i2c_init(struct cyg_i2c_bus* bus) { cyg_zynq_i2c_extra* extra = (cyg_zynq_i2c_extra*)bus->i2c_extra; cyg_uint16 div_a, div_b; cyg_uint16 temp_div_a, temp_div_b; cyg_uint32 error, last_error; cyg_uint32 temp; cyg_uint16 ctrl_reg; extra->i2c_isr_vector = XI2CPS_ISR_VECT; extra->i2c_isr_priority = 0; extra->i2c_hold_flag = 0; // register ISR cyg_drv_mutex_init(&extra->i2c_lock); cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock); cyg_drv_interrupt_create(extra->i2c_isr_vector, extra->i2c_isr_priority, (cyg_addrword_t) extra, &zynq_i2c_isr, &zynq_i2c_dsr, &(extra->i2c_int_handle), &(extra->i2c_int_data)); cyg_drv_interrupt_attach(extra->i2c_int_handle); // Calculate values of diva and divb based o the PCLK and FSCL for(temp_div_a = 0; temp_div_a < 4; temp_div_a++) { //calculate div_b for assumed div_a temp = 22 * extra->i2c_bus_freq * (temp_div_a + 1); temp_div_b = (CYGPKG_DEVS_I2C_ARM_XC7Z_PCLK / temp) - 1; //error = assumed_fscl - calculated_fscl error = extra->i2c_bus_freq - (CYGPKG_DEVS_I2C_ARM_XC7Z_PCLK / (22 * (temp_div_a + 1) * (temp_div_b + 1))); //don't compare errors for first loop iteration if(temp_div_a == 0) { last_error = error; div_a = temp_div_a; div_b = temp_div_b; } else if(last_error < error) //save the best divisors values { div_a = temp_div_a; div_b = temp_div_b; } } #ifdef ZYNQ_I2C_DEBUG DPRINTF("divisors calculated: "); diag_printf("div_a = %d, div_b = %d\n", div_a, div_b); #endif // read actual config HAL_READ_UINT16(XI2CPS_BASE + XI2CPS_CR_OFFSET, ctrl_reg); // clear divisor_a and divisor_b fields ctrl_reg &= ~(0x0000C000 | 0x00003F00); //set new values of divisor_a and divisor_b ctrl_reg |= ((div_a << 14) | (div_b << 8)); // write config HAL_WRITE_UINT16(XI2CPS_BASE + XI2CPS_CR_OFFSET, ctrl_reg); // enable interrupts HAL_WRITE_UINT16(XI2CPS_BASE + XI2CPS_IER_OFFSET, XI2CPS_ENABLED_INTR); // set time-out as long as possible HAL_WRITE_UINT8(XI2CPS_BASE + XI2CPS_TIME_OUT_OFFSET, 0xFF); #ifdef ZYNQ_I2C_DEBUG DPRINTF("init OK\n"); #endif }