void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; cyg_hal_plf_serial_init(); // Defined in hal/powerpc/quicc/... }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; cyg_hal_plf_serial_init(); }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; /* This is where I will put the SCC1 initialization code */ cyg_hal_plf_serial_init(); }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; /* Setup GPIO and enable transceiver for UARTs */ cyg_hal_plf_duart_init(); cyg_hal_plf_serial_init(); }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if(initialized) return; initialized = 1; cyg_hal_plf_serial_init(); #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT2 cyg_hal_gdb_isr_attach(); // FIXME, hack to get CTRLC working #endif }
// // Initialize serial ports - called during hal_if_init() // Note: actual serial port support code is supported by the PPC405 variant layer // Having this call here allows for additional platform specific additions // void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; #if defined(CYGSEM_VIRTEX4_LCD_COMM) && defined(MNDHWR_VIRTEX4_TFT) cyg_hal_plf_lcd_init(); #else cyg_hal_plf_serial_init(); #endif }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; cyg_hal_plf_serial_init(); #ifdef CYGDBG_HAL_V85X_V850_ICE_DIAG cyg_hal_plf_ice_diag_init(); #endif }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; // SuperIO claims channel 0 for the COM1 connector cyg_hal_plf_serial_init(); // Debug connector on mainboard is SCIF2. cyg_hal_plf_scif_init(0, 1, CYGNUM_HAL_INTERRUPT_SCIF_RXI2, (cyg_uint8*)CYGARC_REG_SCIF_SCSMR2); }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; cyg_hal_plf_serial_init(); #if defined(CYGNUM_HAL_AM33_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_SERIAL_CHANNELS > 0 cyg_hal_am33_serial_init(1); #endif }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; // SuperIO claims channels 0-1 for COM1/COM2 connectors on // the back of the chassis. cyg_hal_plf_serial_init(); // Debug connector on mainboard is SCIF2. cyg_hal_plf_scif_init(0, 2, CYGNUM_HAL_INTERRUPT_SCIF_RXI2, (cyg_uint8*)CYGARC_REG_SCIF_SCSMR2); }
void cyg_hal_plf_comms_init(void) { static int initialized = 0; int num_serial; if (initialized) return; initialized = 1; num_serial = CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; #ifdef CYGSEM_HAL_I386_PC_DIAG_SCREEN --num_serial; #endif if (num_serial > 0) { // COM1 pc_ser_channels[0].base = 0x3F8; pc_ser_channels[0].msec_timeout = 1000; pc_ser_channels[0].isr_vector = 36; } if (num_serial > 1) { // COM2 pc_ser_channels[1].base = 0x2F8; pc_ser_channels[1].msec_timeout = 1000; pc_ser_channels[1].isr_vector = 35; } cyg_hal_plf_serial_init(); #ifdef CYGSEM_HAL_I386_PC_DIAG_SCREEN pc_ser_channels[num_serial].base = 0x060; pc_ser_channels[num_serial].msec_timeout = 1000; pc_ser_channels[num_serial].isr_vector = 33; cyg_hal_plf_screen_init(); #endif }
void hal_plf_diag_init(void) { cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); }