static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// CYGACC_CALL_VV1(__call_if_set_console_comm_t*, CYGNUM_CALL_IF_SET_CONSOLE_COMM, -1)
//__call_VV1(CYGNUM_CALL_IF_SET_CONSOLE_COMM, __call_if_set_console_comm_t, int, int)
// Disable interrupts.
HAL_INTERRUPT_MASK(smdk_ser_channels[0].isr_vector);
HAL_INTERRUPT_MASK(smdk_ser_channels[1].isr_vector);
//Unmask UART0/1 RX interrupt
HAL_WRITE_UINT32(INTSUBMSK, __READ_UINT32(INTSUBMSK) & ~(BIT_SUB_RXD0|BIT_SUB_RXD1));
// Init channels
cyg_hal_plf_serial_init_channel(&smdk_ser_channels[0]);
cyg_hal_plf_serial_init_channel(&smdk_ser_channels[1]);
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
int iChannels = sizeof(s_atSerialChannels) / sizeof(s_atSerialChannels[0]);
int iIdx;
for(iIdx = 0; iIdx < iChannels; iIdx++)
{
// Disable interrupts.
HAL_INTERRUPT_MASK(s_atSerialChannels[iIdx].isr_vector);
// Init channels
cyg_hal_plf_serial_init_channel(&s_atSerialChannels[iIdx]);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(iIdx);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &s_atSerialChannels[iIdx]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
channel_data_t* chan;
chan = &aeb_ser_channels[0];
chan->base = (cyg_uint8*)CYG_DEV_UART1_BASE;
chan->isr_vector = CYGNUM_HAL_INTERRUPT_UART1;
chan->msec_timeout = 1000;
// Init channel
cyg_hal_plf_serial_init_channel(chan);
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, chan);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void
cyg_hal_am33_serial_init(int first_chan)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
int i;
for (i = 0; i < AM33_NUM_UARTS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
// Init channel
cyg_hal_plf_serial_init_channel((void*)&channels[i]);
cyg_hal_plf_serial_set_baud(channels[i].base, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(i + first_chan);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
#define NUM_CHANNELS CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS
for (i = 0; i < NUM_CHANNELS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[i].isr_vector);
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[i]);
// Setup procs in the vector table
// Set COMM callbacks for channel
CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void
cyg_hal_ixp425_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
for (i = 0; i < IXP425_NUM_UARTS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(plf_ser_channels[i].isr_vector);
// Init channels
cyg_hal_plf_serial_init_channel(&plf_ser_channels[i]);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Init channels
cyg_hal_plf_serial_init_channel(&aaed2000_ser_channels[0]);
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &aaed2000_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur;
int chan_i;
cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Init channels
for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) {
cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
#endif
}
//===========================================================================
// Initialize serial channel
//===========================================================================
void cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur;
cur =
CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Init channels
cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[0]);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[1]);
#endif
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg |= FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
cyg_uint8 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
chan->irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan->irq_state;
chan->irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
void hal_diag_init(void)
{
static int init = 0;
char *msg = "\n\rARM eCos\n\r";
if (init++) return;
cyg_hal_plf_serial_init_channel(&ns_ser_channel);
while (*msg) cyg_hal_plf_serial_putc(&ns_ser_channel, *msg++);
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
void hal_diag_init(void)
{
static int init = 0;
#ifndef CYG_HAL_STARTUP_ROM
char *msg = "\n\rRAM EDB7XXX eCos\n\r";
#endif
if (init++) return;
cyg_hal_plf_serial_init_channel(&edb_ser_channel);
#ifndef CYG_HAL_STARTUP_ROM
while (*msg) hal_diag_write_char(*msg++);
#endif
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur;
cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
#if 0 /* No interrupts yet */
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
#endif
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[0]);
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#ifdef NOTANYMORE
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void hal_diag_init(void)
{
static int init = 0;
if (init) return;
init++;
// hardwired base
eppc = eppc_base();
// init the actual serial port
cyg_hal_plf_serial_init_channel();
#ifdef CYGSEM_HAL_DIAG_MANGLER_GDB
#ifndef CYG_HAL_STARTUP_ROM
// We are talking to GDB; ack the "go" packet!
cyg_hal_plf_serial_putc(eppc, '+');
#endif
#endif
}
// Initialize diag port
void hal_diag_init(void)
{
// Assume port is already setup
if (0) cyg_hal_plf_serial_init_channel(&edb_ser_channel);
}
// Initialize diag port - assume GDB channel is already set up
void hal_diag_init(void)
{
if (0) cyg_hal_plf_serial_init_channel(&ns_ser_channel); // avoid warning
}
