/*Handler d'IT*/ cyg_uint32 dev_linux_com0_isr(cyg_vector_t vector, cyg_addrword_t data) { /*Blocage d'une IT similaire tant que la DSR ne sait pas exécutée*/ cyg_interrupt_mask(vector); u_int32 _usart_csr; u_int32 _usart_imr; if(_linux_uart_s0_loaded) { do { send_order_r('R', US_CSR, &_usart_csr); send_order_r('R', US_IMR, &_usart_imr); if((_usart_csr&IER_MASK_RCV)==IER_MASK_RCV) { //dev_linux_com0_read(_linux_uart_s0_desc_rd, uart_0_rcv_buffer, 1); dev_linux_com0_rcv(); } if((_usart_csr&IER_MASK_SND)==IER_MASK_SND) { dev_linux_com0_snd(); } } while((_usart_csr & _usart_imr & (IER_MASK_RCV)) || (_usart_csr & _usart_imr & (IER_MASK_SND)) ); } /*ACK de l'IT au CPU*/ cyg_interrupt_acknowledge(vector); /*Informe kernel d'exécuter DSR*/ return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); }
void i2cEnableInterrupt (BOOL bIsEnableINT) { UINT32 regdata; //k09144-1 sysSetInterruptType(IRQ_FI2C, LOW_LEVEL_SENSITIVE); //k08184-1 #ifdef ECOS if (bIsEnableINT) // enable I2C interrupt { cyg_interrupt_create(IRQ_FI2C, 1, 0, Int_Handler_FastI2C, NULL, &int_handle_I2C, &int_holder_I2C); cyg_interrupt_attach(int_handle_I2C); cyg_interrupt_unmask(IRQ_FI2C); } else { cyg_interrupt_mask(IRQ_FI2C); cyg_interrupt_detach(int_handle_I2C); } #else sysInstallISR(IRQ_LEVEL_1, IRQ_FI2C, (PVOID)Int_Handler_FastI2C); //IRQ_FI2C=24 if (bIsEnableINT) sysEnableInterrupt(IRQ_FI2C); //k03224-1 else sysDisableInterrupt (IRQ_FI2C); #endif _i2c_bINT_EN=bIsEnableINT; //k07195-1 //enable sensor I2C engine's interrupt if (bIsEnableINT) { regdata=inpw (REG_FastSerialBusCR)|0x02; outpw (REG_FastSerialBusCR,regdata); } //To clear interrupt status regdata=inpw (REG_FastSerialBusStatus)|0x03; outpw (REG_FastSerialBusStatus,regdata); /* enable I2C interrupt */ //k08204-1 sysEnableInterrupt(IRQ_FI2C); //k03224-1 }
cyg_uint32 dev_at91sam9261_isr(cyg_vector_t vector, cyg_addrword_t data) { volatile unsigned int spi_sr; cyg_interrupt_mask(vector); // le driver est il deja charge? if (dev_at91sam9261_spi_loaded) { //lecture du registre d'etat pour connaitre l'origine de l'IT spi_sr = *AT91C_SPI0_SR; //est ce une it de fin d'emission? if (spi_sr & AT91C_SPI_ENDTX) { // desactivation de l'emetteur et du récepteur *AT91C_SPI0_PTCR = AT91C_PDC_RXTDIS| AT91C_PDC_TXTDIS; //desactivation de l'it ENDTX *AT91C_SPI0_IDR = AT91C_SPI_ENDTX; } } //ACK de l'IT au CPU cyg_interrupt_acknowledge(vector); //appel du DSR return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); }
/*------------------------------------------- | Name:_kinetis_uart_isr | Description: | Parameters: | Return Type: | Comments: | See: ---------------------------------------------*/ cyg_uint32 _kinetis_uart_x_isr(cyg_vector_t vector, cyg_addrword_t data) { cyg_interrupt_mask(vector); cyg_interrupt_acknowledge(vector); _kinetis_uart_stat.isr++; return CYG_ISR_HANDLED | CYG_ISR_CALL_DSR; }
cyg_uint32 dev_at91sam9261_uart_isr(cyg_vector_t vector, cyg_addrword_t data) { cyg_interrupt_mask(vector); dev_at91sam9261_uart_x_interrupt((board_inf_uart_t*)data); cyg_interrupt_acknowledge(vector); //Informe kernel d'exécuter DSR return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); }
/*------------------------------------------- | Name:dev_at91sam9261_spi_close | Description: | Parameters: | Return Type: | Comments: | See: ---------------------------------------------*/ int dev_at91sam9261_spi_close(desc_t desc){ #ifdef USE_DMA_INTERUPT_TRANSMISSION //masquer l'it SPI cyg_interrupt_mask(CYGNUM_HAL_INTERRUPT_SPI0); //supprimer l'IT cyg_interrupt_delete(_at91sam9261_spi_handle); //detruire le semaphore d'attente kernel_sem_destroy(&spi_sem_tx_end); #endif //destruction du timer rttmr_delete(&dev_at91sam9261_spi_timer); }
/*------------------------------------------- | Name : dev_at91sam9260_uart1_isr | Description: | Parameters : None | Return Type: None | Comments : - | See : - ---------------------------------------------*/ cyg_uint32 dev_at91sam9260_uart1_isr(cyg_vector_t vector, cyg_addrword_t data) { cyg_interrupt_mask(vector); unsigned int usart_csr; unsigned int recv_intr_cond = 0; unsigned int trans_intr_cond = 0; board_inf_uart_t *p_inf_uart; AT91S_USART *p_adr; p_inf_uart = (board_inf_uart_t *)ofile_lst[desc_uart1].p; p_adr = (AT91S_USART*)p_inf_uart->base_adr; // if device is loaded if (p_inf_uart->loaded) { do { usart_csr = p_adr->US_CSR; if (p_inf_uart->o_flag & O_RDONLY) { // Overrun Error if ((usart_csr & 0x00000020) == 0x00000020) { // Reset status bits, reset rx/tx. p_adr->US_CR = AT91C_US_RSTSTA; } // Receiver byte per byte if ((usart_csr & 0x01) == 0x01) { // RXRDY //receive fifo dev_at91sam9260_uart_x_fifo_rcv(desc_uart1); } recv_intr_cond = usart_csr & (p_adr->US_IMR) & (0x00000001); } // if (p_inf_uart->o_flag & O_WRONLY) { // TXRDY if (((usart_csr & 0x00000002) == 0x00000002) && (p_inf_uart->XMIT)) { //Transmission (per byte) dev_at91sam9260_uart_x_snd(desc_uart1); } trans_intr_cond = ( (p_inf_uart->XMIT) && (usart_csr & (p_adr->US_IMR) & (0x00000002))); } } while ( recv_intr_cond || trans_intr_cond ); } // Timer Value initialization for Read p_inf_uart->inter_char_timer = p_inf_uart->ttys_termios.c_cc[VTIME]; //ACK de l'IT au CPU cyg_interrupt_acknowledge(vector); //Informe kernel d'ex�cuter DSR return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); }
/*------------------------------------------- | Name:dev_k60n512_uart_x_read | Description: | Parameters: | Return Type: | Comments: | See: ---------------------------------------------*/ int dev_k60n512_uart_x_read(desc_t desc, char* buf,int size) { board_kinetis_uart_info_t * p_uart_info = (board_kinetis_uart_info_t*)ofile_lst[desc].p; int cb = 0; int count = 0; cb = (size>=UART_RX_BUFFER_SIZE) ? UART_RX_BUFFER_SIZE : size; cyg_interrupt_mask((cyg_vector_t)p_uart_info->irq_no); // while(p_uart_info->input_r != p_uart_info->input_w && count < cb) { buf[count++] = p_uart_info->input_buffer[p_uart_info->input_r]; p_uart_info->input_r = (p_uart_info->input_r+1) & (UART_RX_BUFFER_SIZE-1); } // cyg_interrupt_unmask((cyg_vector_t)p_uart_info->irq_no); return count; }
cyg_uint32 dev_linux_eth_isr(cyg_vector_t vector, cyg_addrword_t data) { //Blocage d'une IT similaire tant que la DSR ne sait pas exécutée cyg_interrupt_mask(vector); // if(data==OPS_READ) { dev_linux_eth_rcv(); } if(data==OPS_WRITE) { dev_linux_eth_snd(); } //ACK de l'IT au CPU cyg_interrupt_acknowledge(vector); //Informe kernel d'exécuter DSR return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); }
void capInit(BOOL bCapEngEnable, BOOL bCapIntEnable) #endif { int j; int i=sizeof(VCEInit)/sizeof(T_REG_INFO); for (j=0; j<i ;j++) outpw((CAP_BA+VCEInit[j].uAddr),VCEInit[j].uValue); if(bCapEngEnable==TRUE) { outpw(REG_CAPEngine,inpw(REG_CAPEngine)|0x01); } else { outpw(REG_CAPEngine,inpw(REG_CAPEngine)&0xfffffffe); } if(bCapIntEnable==TRUE) { #ifdef ECOS cyg_interrupt_disable(); cyg_interrupt_create(IRQ_VCE, 1, 0, capIntHandler, capIntHandlerDSR, &(t_eCos->cap_int_handle), &(t_eCos->cap_int)); cyg_interrupt_attach(t_eCos->cap_int_handle); cyg_interrupt_unmask(IRQ_VCE); cyg_interrupt_enable(); #else sysInstallISR(IRQ_LEVEL_1, IRQ_VCE, (PVOID)capIntHandler); // sysEnableInterrupt(IRQ_VCE); #endif outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x2); } else { #ifdef ECOS cyg_interrupt_mask(IRQ_VCE); cyg_interrupt_detach(t_eCos->cap_int_handle); cyg_interrupt_delete(t_eCos->cap_int_handle); #else sysDisableInterrupt(IRQ_VCE); #endif outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffffd); } }
INT w5691StopPlay() { #ifdef SOFT_MODE INT bytes; #endif const UINT8 abyCmdStopSpeech[] = { 0x03, 0x04, 0x02 }; #ifdef ECOS cyg_interrupt_mask(GPIO_INT_NUM); cyg_interrupt_detach(_tW5691.int_handle_play); #else sysDisableInterrupt(GPIO_INT_NUM); #endif #ifdef SOFT_MODE //outpw(REG_ACTL_M80CON, 0x25202); outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) | W_GFIFO ); soft_write_command_byte_reg(0x08); soft_write_data_reg(0x55); for (bytes=0;bytes<3;bytes++){ soft_write_data_reg(abyCmdStopSpeech[bytes]); } //outpw(REG_ACTL_M80CON, 0x5202); outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) & ~W_GFIFO ); #else outpw(REG_ACTL_M80SIZE, sizeof(abyCmdStopSpeech)+1); outpw(REG_ACTL_M80DATA0, 0x55 | abyCmdStopSpeech[0]<<8 | (abyCmdStopSpeech[1]<<16) | (abyCmdStopSpeech[2]<<24) ); outpw(REG_ACTL_M80ADDR, 0x08); //outpw(REG_ACTL_M80CON, 0x25210); outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) | W_GFIFO | W_IF12_ACT); while((inpw(REG_ACTL_M80CON)&W_IF12_ACT) != 0); //outpw(REG_ACTL_M80CON, 0x5200); outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) & ~W_GFIFO ); #endif ComDrv_SendCommand(eCOMMAND_DISABLE_SPEECH_INTERRUPT); DevDrv_PowerDown(); _W5691_Playing = 0; return 0; }
void capIntHandler(void) #endif { UCHAR ucBuf; #ifdef ECOS cyg_interrupt_mask(vector); #endif _cap_uFrame=_cap_uFrame+1; if(inpw(REG_CAPFuncEnable)&0x10) {//Dual Buffer enable if(inpw(REG_CAPFuncEnable)&0x40) {//will use the buffer 0 for VPOST & JPEG outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xffffff9F); ucBuf=0; } else {//will use the buffer 1 for VPOST & JPEG outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00000060); ucBuf=1; } } //Call back to the function written by user. outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)); #ifndef ECOS if(CapIntHandlerTable[0]!=0) { UCHAR ucfr; ucfr=(inpw(REG_CAPFuncEnable)&0x04) ? TRUE:FALSE; CapIntHandlerTable[0](ucBuf,ucBuf,ucfr, FALSE); } #endif #ifdef ECOS cyg_interrupt_acknowledge(vector); //important return CYG_ISR_CALL_DSR; #endif }
// This ISR is called when a CompactFlash board is inserted static int cf_detect_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { cyg_interrupt_mask(SA1110_CF_DETECT); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
void kintr0_main( void ) { cyg_vector_t v = (CYGNUM_HAL_VSR_MIN + 11) % CYGNUM_HAL_VSR_COUNT; cyg_vector_t v1; cyg_vector_t lvl1 = CYGNUM_HAL_ISR_MIN + (1 % CYGNUM_HAL_ISR_COUNT); cyg_vector_t lvl2 = CYGNUM_HAL_ISR_MIN + (15 % CYGNUM_HAL_ISR_COUNT); int in_use; cyg_VSR_t *old_vsr, *new_vsr; CYG_TEST_INIT(); #ifdef CYGPKG_HAL_MIPS_TX39 // This can be removed when PR 17831 is fixed if ( cyg_test_is_simulator ) v1 = 12 % CYGNUM_HAL_ISR_COUNT; else /* NOTE TRAILING ELSE... */ #endif v1 = CYGNUM_HAL_ISR_MIN + ( 6 % CYGNUM_HAL_ISR_COUNT); CHECK(flash()); CHECK(flash()); // Make sure the chosen levels are not already in use. HAL_INTERRUPT_IN_USE( lvl1, in_use ); intr0 = 0; if (!in_use) cyg_interrupt_create(lvl1, PRIO_B, (cyg_addrword_t)777, isr0, dsr0, &intr0, &intr_obj[0]); HAL_INTERRUPT_IN_USE( lvl2, in_use ); intr1 = 0; if (!in_use && lvl1 != lvl2) cyg_interrupt_create(lvl2, PRIO_C, 888, isr1, dsr1, &intr1, &intr_obj[1]); // Check these functions at least exist cyg_interrupt_disable(); cyg_interrupt_enable(); if (intr0) cyg_interrupt_attach(intr0); if (intr1) cyg_interrupt_attach(intr1); if (intr0) cyg_interrupt_detach(intr0); if (intr1) cyg_interrupt_detach(intr1); // If this attaching interrupt replaces the previous interrupt // instead of adding to it we could be in a big mess if the // vector is being used by something important. cyg_interrupt_get_vsr( v, &old_vsr ); cyg_interrupt_set_vsr( v, vsr0 ); cyg_interrupt_get_vsr( v, &new_vsr ); CHECK( vsr0 == new_vsr ); new_vsr = NULL; cyg_interrupt_get_vsr( v, &new_vsr ); cyg_interrupt_set_vsr( v, old_vsr ); CHECK( new_vsr == vsr0 ); cyg_interrupt_set_vsr( v, new_vsr ); new_vsr = NULL; cyg_interrupt_get_vsr( v, &new_vsr ); CHECK( vsr0 == new_vsr ); cyg_interrupt_set_vsr( v, old_vsr ); CHECK( vsr0 == new_vsr ); new_vsr = NULL; cyg_interrupt_get_vsr( v, &new_vsr ); CHECK( old_vsr == new_vsr ); CHECK( NULL != vsr0 ); cyg_interrupt_mask(v1); cyg_interrupt_unmask(v1); cyg_interrupt_configure(v1, true, true); CYG_TEST_PASS_FINISH("Kernel C API Intr 0 OK"); }
// Serial I/O - low level interrupt handler (ISR) static cyg_uint32 ra305x_timer0_isr(cyg_vector_t vector, cyg_addrword_t data) { cyg_interrupt_mask(CYGNUM_HAL_INTERRUPT_TIMER0); cyg_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_TIMER0); return CYG_ISR_CALL_DSR; // Cause DSR to be run }
cyg_uint32 dev_at91sam9261_uart_dbg_isr(cyg_vector_t vector, cyg_addrword_t data) { cyg_interrupt_mask(vector); unsigned int usart_csr; unsigned int recv_intr_cond = 0; unsigned int trans_intr_cond = 0; board_inf_uart_t *p_inf_uart; AT91_REG *p_adr; desc_t desc_r; desc_t desc_w; p_inf_uart = (board_inf_uart_t *)ofile_lst[desc_uart_dbg].p; p_adr = (AT91_REG *)p_inf_uart->base_adr; desc_r = p_inf_uart->desc_r; desc_w = p_inf_uart->desc_w; // if device is loaded if (p_inf_uart->loaded) { do { usart_csr = *(p_adr+US_CSR); if( (desc_r>=0) && (ofile_lst[desc_r].oflag & O_RDONLY) ) { // Overrun Error if ((usart_csr & 0x00000020) == 0x00000020) { // Reset status bits, reset rx/tx. *(p_adr+US_CR) = AT91C_US_RSTSTA; // old value 0x00000100; } // Receiver byte per byte if ((usart_csr & 0x01) == 0x01) // RXRDY { //receive fifo dev_at91sam9261_uart_dbg_x_fifo_rcv(desc_uart_dbg); } recv_intr_cond = usart_csr & *(p_adr+US_IMR) & (0x00000001); } // if( (desc_w>=0) && (ofile_lst[desc_w].oflag & O_WRONLY) ) { // TXRDY if (((usart_csr & 0x00000002) == 0x00000002) && (p_inf_uart->XMIT)) { //Transmission (per byte) //dev_at91sam9261_uart_x_snd(desc); dev_at91sam9261_uart_dbg_x_snd(desc_uart_dbg); } // trans_intr_cond = ( (p_inf_uart->XMIT) && (usart_csr & *(p_adr+US_IMR) & (0x00000002))); } } while ( recv_intr_cond || trans_intr_cond ); } // Timer Value initialization for Read p_inf_uart->inter_char_timer=ttys_termios.c_cc[VTIME]; //*AT91C_AIC_EOICR = 0; // Signal end of interrupt to AIC. //ACK de l'IT au CPU cyg_interrupt_acknowledge(vector); //Informe kernel d'exécuter DSR return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); }