void
cyg_hal_plf_pci_init(void)
{
cyg_uint32 dram_limit = (0xFFFFFFFF - (hal_dram_size - 1)) & 0xFFFFFFC0;
// Enable NIC through GPIO pin. This may not have an effect depending
// on switch settings.
*GPIO_GPOE &= ~(1 << IQ80321_GBE_GPIO_PIN);
*GPIO_GPOD |= (1 << IQ80321_GBE_GPIO_PIN);
hal_pci_inbound_window_mask = ~dram_limit;
// Force BAR0 to be non-prefetchable to allow proper MU usage
*ATU_IABAR0 &= ~CYG_PRI_CFG_BAR_MEM_PREFETCH;
#ifdef CYG_HAL_STARTUP_ROM
#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
if (!hal_pcsr_cfg_retry || !cyg_hal_plf_wait_for_bios())
#endif // CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
{
// 64-bit prefetchable
*ATU_IABAR2 = SDRAM_PHYS_BASE | \
CYG_PRI_CFG_BAR_MEM_TYPE_64 | \
CYG_PRI_CFG_BAR_MEM_PREFETCH;
*ATU_IAUBAR2 = 0;
// Outbound window will be set based on the memory reserved
// by inbound window 1
*ATU_IABAR1 = _PCI_MEM_BASE | \
CYG_PRI_CFG_BAR_MEM_TYPE_64 | \
CYG_PRI_CFG_BAR_MEM_PREFETCH;
}
#endif // CYG_HAL_STARTUP_ROM
// allow ATU to act as a bus master, respond to PCI memory accesses,
// and assert S_SERR#
*ATU_ATUCMD = (CYG_PCI_CFG_COMMAND_SERR | \
CYG_PCI_CFG_COMMAND_PARITY | \
CYG_PCI_CFG_COMMAND_MASTER | \
CYG_PCI_CFG_COMMAND_MEMORY);
hal_pci_alloc_base_memory = *ATU_IABAR1 & CYG_PRI_CFG_BAR_MEM_MASK;
hal_pci_alloc_base_io = _PCI_IO_BASE;
hal_pci_inbound_window_base = *ATU_IABAR2 & CYG_PRI_CFG_BAR_MEM_MASK;
// set the outbound window PCI address
*ATU_OMWTVR0 = hal_pci_alloc_base_memory;
*ATU_OUMWTVR0 = 0;
// outbound I/O window
*ATU_OIOWTVR = hal_pci_alloc_base_io;
hal_pci_physical_memory_base = _PCI_MEM_BASE - hal_pci_alloc_base_memory;
hal_pci_physical_io_base = _PCI_IO_BASE - hal_pci_alloc_base_io;
#ifdef CYG_HAL_MEMORY_MAP_NORMAL
// Adjust for Virt - Phys in CPU space
hal_pci_physical_memory_base += 0x20000000;
hal_pci_physical_io_base += 0x20000000;
#endif
cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY);
cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
// enable outbound ATU
*ATU_ATUCR = 2;
*ATU_APMCSR = 3;
}
void cyg_hal_plf_pci_init(void)
{
cyg_uint32 limit_reg, adj_dram_size;
cyg_uint8 next_bus;
// Initialize Secondary PCI bus (bus 1)
*(volatile cyg_uint16 *)BCR_ADDR |= 0x40; // reset secondary bus
hal_delay_us(10 * 1000); // 10ms enough??
*(volatile cyg_uint16 *)BCR_ADDR &= ~0x40; // release reset
// ********* vendor / device id **********
*(cyg_uint16 *)ASVIR_ADDR = 0x113C;
*(cyg_uint16 *)ASIR_ADDR = 0x0700;
// suppress secondary bus idsels to provide private secondary devices
*(cyg_uint16 *)SISR_ADDR = 0x03FF;
// ******* Primary Inbound ATU *********
// set primary inbound ATU translate value register to point to
// base of local DRAM
*(cyg_uint32 *)PIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC;
// set primary inbound ATU limit register to include all of installed DRAM.
// This value used as a mask.
adj_dram_size = hal_dram_size;
limit_reg = (0xFFFFFFFF-(adj_dram_size-1)) & 0xFFFFFFF0;
*(cyg_uint32 *)PIALR_ADDR = limit_reg;
if (iq80310_is_host()) {
// set the primary inbound ATU base address to the start of DRAM
*(cyg_uint32 *)PIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000;
// ********* Set Primary Outbound Windows *********
// Note: The primary outbound ATU memory window value register
// and i/o window value registers are defaulted to 0
// set the primary outbound windows to directly map Local - PCI
// requests
// outbound memory window
*(cyg_uint32 *)POMWVR_ADDR = PRIMARY_MEM_BASE;
// outbound DAC Window
*(cyg_uint32 *)PODWVR_ADDR = PRIMARY_DAC_BASE;
// outbound I/O window
*(cyg_uint32 *)POIOWVR_ADDR = PRIMARY_IO_BASE;
}
#ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY
// clear RETRY
*(cyg_uint16 *)EBCR_ADDR = 0x0008;
#endif
// ******** Secondary Inbound ATU ***********
// set secondary inbound ATU translate value register to point to base
// of local DRAM
*(cyg_uint32 *)SIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC;
// set secondary inbound ATU base address to start of DRAM
*(cyg_uint32 *)SIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000;
// set secondary inbound ATU limit register to include all of
// installed DRAM. This value used as a mask.
// always allow secondary pci access to all memory (even with A0 step)
limit_reg = (0xFFFFFFFF - (adj_dram_size - 1)) & 0xFFFFFFF0;
*(cyg_uint32 *)SIALR_ADDR = limit_reg;
// ********** Set Secondary Outbound Windows ***********
// Note: The secondary outbound ATU memory window value register
// and i/o window value registers are defaulted to 0
// set the secondary outbound window to directly map Local - PCI requests
// outbound memory window
*(cyg_uint32 *)SOMWVR_ADDR = SECONDARY_MEM_BASE;
// outbound DAC Window
*(cyg_uint32 *)SODWVR_ADDR = SECONDARY_DAC_BASE;
// outbound I/O window
*(cyg_uint32 *)SOIOWVR_ADDR = SECONDARY_IO_BASE;
// *********** command / config / latency registers ************
if (iq80310_is_host()) {
// allow primary ATU to act as a bus master, respond to PCI
// memory accesses, assert P_SERR#, and enable parity checking
*(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
CYG_PCI_CFG_COMMAND_PARITY | \
CYG_PCI_CFG_COMMAND_MASTER | \
CYG_PCI_CFG_COMMAND_MEMORY);
}
// allow secondary ATU to act as a bus master, respond to PCI memory
// accesses, and assert S_SERR#
*(cyg_uint16 *)SATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
CYG_PCI_CFG_COMMAND_PARITY | \
CYG_PCI_CFG_COMMAND_MASTER | \
CYG_PCI_CFG_COMMAND_MEMORY);
// enable primary and secondary outbound ATUs, BIST, and primary bus
// direct addressing
*(cyg_uint32 *)ATUCR_ADDR = 0x00000006;
// ************ bridge registers *******************
if (iq80310_is_host()) {
// set the bridge command register
*(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
CYG_PCI_CFG_COMMAND_PARITY | \
CYG_PCI_CFG_COMMAND_MASTER | \
CYG_PCI_CFG_COMMAND_MEMORY);
// set the secondary bus number to 1
*(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
*(cyg_uint16 *)BCR_ADDR = 0x0823;
// set the primary bus number to 0
*(cyg_uint8 *)PBNR_ADDR = PRIMARY_BUS_NUM;
} else {
#ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY
// Wait for PC BIOS to initialize bus number
int i;
for (i = 0; i < 15000; i++) {
if (*((volatile cyg_uint8 *)SBNR_ADDR) != 0)
break;
hal_delay_us(1000); // 1msec
}
#endif
if (*((volatile cyg_uint8 *)SBNR_ADDR) == 0)
*(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
}
pbus_nr = *(cyg_uint8 *)PBNR_ADDR;
sbus_nr = *(cyg_uint8 *)SBNR_ADDR;
// Now initialize the PCI busses.
// Next assignable bus number. Yavapai primary bus is fixed as
// bus zero and yavapai secondary is fixed as bus 1.
next_bus = sbus_nr + 1;
// If we are the host on the Primary bus, then configure it.
if (iq80310_is_host()) {
// Initialize Primary PCI bus (bus 0)
cyg_pci_set_memory_base(PRIMARY_MEM_BASE);
cyg_pci_set_io_base(PRIMARY_IO_BASE);
cyg_pci_configure_bus(0, &next_bus);
}
// Initialize Secondary PCI bus (bus 1)
cyg_pci_set_memory_base(SECONDARY_MEM_BASE);
cyg_pci_set_io_base(SECONDARY_IO_BASE);
cyg_pci_configure_bus(sbus_nr, &next_bus);
}
