/**
* \brief DACC configuration.
*/
static void dsp_configure_dacc(void)
{
pmc_enable_periph_clk(ID_DACC);
/*
* DACC setting
* -Refresh Period = 1024*REFRESH/DACC Clock
* -No max Speed Mode
* -Startup time of 0 periods of DACClock
*/
dacc_set_timing(DACC, DACC_REFRESH, 0, DACC_MR_STARTUP_0);
/* Set TIO Output of TC Channel 1 as trigger */
dacc_set_trigger(DACC,2);
/* Set to half word transfer */
dacc_set_transfer_mode(DACC, DACC_MR_WORD_HALF);
#if (SAM3S) || (SAM3XA)
/* Set to No Sleep Mode and No Fast Wake Up Mode*/
dacc_set_power_save(DACC, 0, 0);
#endif
/* Select both left/right speaker channels. */
dacc_set_channel_selection(DACC, SPEAKER_CHANNEL_R);
dacc_set_channel_selection(DACC, SPEAKER_CHANNEL_L);
/* Enable DACC channels. */
dacc_enable_channel(DACC, SPEAKER_CHANNEL_R);
dacc_enable_channel(DACC, SPEAKER_CHANNEL_L);
/* Tag selection mode enabled. */
dacc_enable_flexible_selection(DACC);
/* Get board DACC PDC base address. */
dacc_pdc = dacc_get_pdc_base(DACC);
/* Enable DACC interrupt. */
dacc_enable_interrupt(DACC,DACC_IER_ENDTX);
NVIC_SetPriority(DACC_IRQn, INT_PRIORITY_DACC);
NVIC_EnableIRQ(DACC_IRQn);
}
void DACClass::begin(uint32_t period) {
// Enable clock for DAC
pmc_enable_periph_clk(dacId);
dacc_reset(dac);
// Set transfer mode to double word
dacc_set_transfer_mode(dac, 1);
// Power save:
// sleep mode - 0 (disabled)
// fast wakeup - 0 (disabled)
dacc_set_power_save(dac, 0, 0);
// DAC refresh/startup timings:
// refresh - 0x08 (1024*8 dacc clocks)
// max speed mode - 0 (disabled)
// startup time - 0x10 (1024 dacc clocks)
dacc_set_timing(dac, 0x08, 0, DACC_MR_STARTUP_1024);
// Flexible channel selection with tags
dacc_enable_flexible_selection(dac);
// Set up analog current
dacc_set_analog_control(dac,
DACC_ACR_IBCTLCH0(0x02) |
DACC_ACR_IBCTLCH1(0x02) |
DACC_ACR_IBCTLDACCORE(0x01));
// Enable output channels
dacc_enable_channel(dac, 0);
dacc_enable_channel(dac, 1);
// Configure Timer Counter to trigger DAC
// --------------------------------------
pmc_enable_periph_clk(ID_TC1);
TC_Configure(TC0, 1,
TC_CMR_TCCLKS_TIMER_CLOCK2 | // Clock at MCR/8
TC_CMR_WAVE | // Waveform mode
TC_CMR_WAVSEL_UP_RC | // Counter running up and reset when equals to RC
TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR);
const uint32_t TC = period / 8;
TC_SetRA(TC0, 1, TC / 2);
TC_SetRC(TC0, 1, TC);
TC_Start(TC0, 1);
// Configure clock source for DAC (2 = TC0 Output Chan. 1)
dacc_set_trigger(dac, 2);
// Configure pins
PIO_Configure(g_APinDescription[DAC0].pPort,
g_APinDescription[DAC0].ulPinType,
g_APinDescription[DAC0].ulPin,
g_APinDescription[DAC0].ulPinConfiguration);
PIO_Configure(g_APinDescription[DAC1].pPort,
g_APinDescription[DAC1].ulPinType,
g_APinDescription[DAC1].ulPin,
g_APinDescription[DAC1].ulPinConfiguration);
// Enable interrupt controller for DAC
dacc_disable_interrupt(dac, 0xFFFFFFFF);
NVIC_DisableIRQ(isrId);
NVIC_ClearPendingIRQ(isrId);
NVIC_SetPriority(isrId, 0);
NVIC_EnableIRQ(isrId);
}
