int dm646x_pll1_init(struct device *dev, void __iomem *base) { struct clk *clk; davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc"); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); clk_register_clkdev(clk, "pll1_sysclk2", "dm646x-psc"); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); clk_register_clkdev(clk, "pll1_sysclk3", "dm646x-psc"); clk_register_clkdev(clk, NULL, "davinci-wdt"); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base); clk_register_clkdev(clk, "pll1_sysclk4", "dm646x-psc"); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base); clk_register_clkdev(clk, "pll1_sysclk5", "dm646x-psc"); davinci_pll_sysclk_register(dev, &pll1_sysclk6, base); davinci_pll_sysclk_register(dev, &pll1_sysclk8, base); davinci_pll_sysclk_register(dev, &pll1_sysclk9, base); davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base); davinci_pll_auxclk_register(dev, "pll1_auxclk", base); return 0; }
int dm646x_pll2_init(struct device *dev, void __iomem *base) { davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base); davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); return 0; }
int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip); davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc"); davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base); return 0; }
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0"); clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1"); clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0"); clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1"); davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0"); davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); davinci_pll_auxclk_register(dev, "pll0_auxclk", base); clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk", CLK_IS_CRITICAL, 1, 1); clk_register_clkdev(clk, NULL, "i2c_davinci.1"); clk_register_clkdev(clk, "timer0", NULL); clk_register_clkdev(clk, NULL, "davinci-wdt"); davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base); return 0; }