void ddb_local0_irqdispatch(struct pt_regs *regs)
{
u32 mask;
int nile4_irq;
#if 1
volatile static int nesting = 0;
if (nesting++ == 0)
ddb5074_led_d3(1);
ddb5074_led_hex(nesting < 16 ? nesting : 15);
#endif
mask = nile4_get_irq_stat(0);
nile4_clear_irq_mask(mask);
/* Handle the timer interrupt first */
if (mask & (1 << NILE4_INT_GPT)) {
nile4_disable_irq(NILE4_INT_GPT);
do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
nile4_enable_irq(NILE4_INT_GPT);
mask &= ~(1 << NILE4_INT_GPT);
}
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
if (mask & 1) {
nile4_disable_irq(nile4_irq);
if (nile4_irq == NILE4_INT_INTE) {
int i8259_irq = nile4_i8259_iack();
i8259_do_irq(i8259_irq, regs);
} else
do_IRQ(nile4_to_irq(nile4_irq), regs);
nile4_enable_irq(nile4_irq);
}
#if 1
if (--nesting == 0)
ddb5074_led_d3(0);
ddb5074_led_hex(nesting < 16 ? nesting : 15);
#endif
}
void __init arch_init_irq(void)
{
/* setup cascade interrupts */
setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
set_except_vector(0, ddbIRQ);
nile4_irq_setup(NILE4_IRQ_BASE);
m1543_irq_setup();
init_i8259_irqs();
printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
mips_cpu_irq_init(CPU_IRQ_BASE);
printk("enabling 8259 cascade\n");
ddb5074_led_hex(0);
/* Enable the interrupt cascade */
nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
}
