void decon_t_set_clocks(struct decon_device *decon)
{
struct device *dev = decon->dev;
struct decon_clocks clks;
struct decon_param p;
decon_to_init_param(decon, &p);
decon_reg_get_clock_ratio(&clks, p.lcd_info);
/* ECLK */
decon_clk_set_rate(dev, decon->res.eclk,
NULL, clks.decon[CLK_ID_ECLK] * MHZ);
decon_clk_set_rate(dev, decon->res.eclk_leaf,
NULL, clks.decon[CLK_ID_ECLK] * MHZ);
#if defined(CONFIG_EXYNOS8890_BTS_OPTIMIZATION)
/* TODO: hard-coded 42 will be changed
* default MIC factor is 3, So default VCLK is 42 for calculating DISP */
decon->vclk_factor = 42 * DECON_PIX_PER_CLK;
#endif
decon_dbg("%s: pclk %ld eclk %ld Mhz\n",
__func__,
clk_get_rate(decon->res.pclk) / MHZ,
clk_get_rate(decon->res.eclk_leaf) / MHZ);
return;
}
void decon_int_set_clocks(struct decon_device *decon)
{
struct device *dev = decon->dev;
u32 clk_val_dpll = decon->pdata->disp_pll_clk;
u32 clk_val_vclk, clk_val_pclk, clk_val_eclk, clk_val_aclk;
if (!clk_val_dpll) {
decon_info("setting predefined clock values\n");
/* predefined values */
decon_clk_set_rate(dev, "disp_pll", 267 * MHZ);
decon_clk_set_rate(dev, "d_pclk_disp", 134 * MHZ);
decon_clk_set_parent(dev, "m_decon0_eclk", "disp_pll");
decon_clk_set_rate(dev, "d_decon0_eclk", 134 * MHZ);
decon_clk_set_parent(dev, "m_decon0_vclk", "disp_pll");
decon_clk_set_rate(dev, "d_decon0_vclk", 134 * MHZ);
} else {
clk_val_vclk = clk_val_dpll>>1;
clk_val_eclk = (clk_val_vclk * 12) / 10;
clk_val_aclk = clk_get_rate(decon->res.aclk_disp_200);
clk_val_pclk = clk_val_aclk>>1;
decon_info("setting pll to %dMHz\n", clk_val_dpll/MHZ);
decon_info("setting clk_val_vclk %dMHz\n", clk_val_vclk/MHZ);
decon_info("setting clk_val_eclk %dMHz\n", clk_val_eclk/MHZ);
decon_info("setting clk_val_aclk %dMHz\n", clk_val_aclk/MHZ);
decon_info("setting clk_val_pclk %dMHz\n", clk_val_pclk/MHZ);
/* values based on DT input */
decon_clk_set_rate(dev, "disp_pll", clk_val_dpll);
decon_clk_set_rate(dev, "d_pclk_disp", clk_val_pclk);
decon_clk_set_parent(dev, "m_decon0_eclk", "m_eclk_user");
decon_clk_set_parent(dev, "m_eclk_user_a",
"m_bus_pll_top_user");
decon_clk_set_rate(dev, "d_sclk_decon0_eclk", clk_val_eclk);
decon_clk_set_rate(dev, "d_decon0_eclk", clk_val_eclk);
decon_clk_set_parent(dev, "m_decon0_vclk", "disp_pll");
decon_clk_set_rate(dev, "d_decon0_vclk", clk_val_vclk);
}
}
void decon_ext_set_clocks(struct decon_device *decon)
{
struct device *dev = decon->dev;
if (decon->out_type == DECON_OUT_HDMI) {
decon_clk_set_parent(dev, "m_decon1_eclk", "um_decon1_eclk");
decon_clk_set_rate(dev, "d_decon1_eclk", 200 * MHZ);
decon_clk_set_parent(dev, "m_decon1_vclk", "hdmi_pixel");
} else if (decon->out_type == DECON_OUT_WB) {
decon_clk_set_parent(dev, "m_decon1_eclk", "um_decon1_eclk");
decon_clk_set_rate(dev, "d_decon1_eclk", 200 * MHZ);
decon_clk_set_parent(dev, "um_decon1_vclk", "disp_pll");
decon_clk_set_rate(dev, "d_decon1_vclk", 134 * MHZ);
decon_clk_set_parent(dev, "m_decon1_vclk", "d_decon1_vclk");
} else if (decon->out_type == DECON_OUT_DSI) {
/* NOTE: It depends on LCD resolution. default is FHD */
/* ECLK(100Mhz) : using BUS0 PLL */
decon_clk_set_parent(dev, "mout_sclk_decon_ext_eclk", "mout_bus0_pll_top0");
decon_clk_set_rate(dev, "dout_sclk_decon_ext_eclk", 100 * MHZ);
decon_clk_set_parent(dev, "m_decon1_eclk", "um_decon1_eclk");
decon_clk_set_rate(dev, "d_decon1_eclk", 100 * MHZ);
/* VCLK(142Mhz) : using DISP PLL */
/* decon-int already configures DISP PLL as 142Mhz */
decon_clk_set_parent(dev, "um_decon1_vclk", "disp_pll");
if (decon->lcd_info->mic_enabled)
decon_clk_set_rate(dev, "d_decon1_vclk", 72 * MHZ);
else
decon_clk_set_rate(dev, "d_decon1_vclk", 143 * MHZ);
decon_clk_set_parent(dev, "m_decon1_vclk", "d_decon1_vclk");
} else {
decon_err("%s: failed to find output device of decon%d\n",
__func__, decon->id);
}
}