void decon_reg_init_probe(struct decon_init_param *p)
{
struct decon_lcd *lcd_info = p->lcd_info;
struct decon_psr_info *psr = &p->psr;
decon_reg_set_clkgate_mode(1);
decon_reg_blend_alpha_bits(BLENDCON_NEW_8BIT_ALPHA_VALUE);
decon_reg_set_vidout(psr->psr_mode, 1);
if (psr->psr_mode == S3C_FB_MIPI_COMMAND_MODE)
decon_reg_set_fixvclk(DECON_VCLK_RUN_VDEN_DISABLE);
else
decon_reg_set_fixvclk(DECON_VCLK_HOLD);
/* RGB order -> porch values -> LINECNT_OP_THRESHOLD -> clock divider
* -> freerun mode --> stop DECON */
decon_reg_set_rgb_order(DECON_RGB);
decon_reg_set_porch(lcd_info);
if (lcd_info->mode == VIDEO_MODE)
decon_reg_set_linecnt_op_threshold(lcd_info->yres - 1);
decon_reg_set_clkval(0);
decon_reg_set_freerun_mode(1);
decon_reg_update_standalone();
if (psr->psr_mode == S3C_FB_MIPI_COMMAND_MODE)
decon_reg_configure_trigger(psr->trig_mode);
decon_reg_set_sys_reg();
}
int decon_set_par(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct decon_win *win = info->par;
struct decon_device *decon = win->decon;
struct decon_regs_data win_regs;
int win_no = win->index;
memset(&win_regs, 0, sizeof(struct decon_regs_data));
dev_info(decon->dev, "setting framebuffer parameters\n");
if (decon->state == DECON_STATE_OFF)
return 0;
decon_lpd_block_exit(decon);
decon_reg_shadow_protect_win(decon->id, win->index, 1);
info->fix.visual = fb_visual(var->bits_per_pixel, 0);
info->fix.line_length = fb_linelength(var->xres_virtual,
var->bits_per_pixel);
info->fix.xpanstep = fb_panstep(var->xres, var->xres_virtual);
info->fix.ypanstep = fb_panstep(var->yres, var->yres_virtual);
if (decon_reg_is_win_enabled(decon->id, win_no))
win_regs.wincon = WINCON_ENWIN;
else
win_regs.wincon = 0;
win_regs.wincon |= wincon(var->bits_per_pixel, var->transp.length);
win_regs.winmap = 0x0;
win_regs.vidosd_a = vidosd_a(0, 0);
win_regs.vidosd_b = vidosd_b(0, 0, var->xres, var->yres);
win_regs.vidosd_c = vidosd_c(0x0, 0x0, 0x0);
win_regs.vidosd_d = vidosd_d(0xff, 0xff, 0xff);
win_regs.vidw_buf_start = info->fix.smem_start;
win_regs.vidw_whole_w = var->xoffset + var->width;
win_regs.vidw_whole_h = var->yoffset + var->height;
win_regs.vidw_offset_x = var->xoffset;
win_regs.vidw_offset_y = var->yoffset;
if (win_no)
win_regs.blendeq = BLENDE_A_FUNC(BLENDE_COEF_ONE) |
BLENDE_B_FUNC(BLENDE_COEF_ZERO) |
BLENDE_P_FUNC(BLENDE_COEF_ZERO) |
BLENDE_Q_FUNC(BLENDE_COEF_ZERO);
win_regs.type = IDMA_G0;
decon_reg_set_regs_data(decon->id, win_no, &win_regs);
decon_reg_shadow_protect_win(decon->id, win->index, 0);
decon_reg_update_standalone(decon->id);
decon_lpd_unblock(decon);
return 0;
}
void decon_reg_start(struct decon_psr_info *psr)
{
decon_reg_direct_on_off(1);
decon_reg_update_standalone();
if ((psr->psr_mode == S3C_FB_MIPI_COMMAND_MODE) &&
(psr->trig_mode == DECON_HW_TRIG))
decon_reg_set_trigger(psr->trig_mode, DECON_TRIG_ENABLE);
}
void decon_reg_configure_lcd(struct decon_lcd *lcd_info)
{
decon_reg_set_rgb_order(DECON_RGB);
decon_reg_set_porch(lcd_info);
if (lcd_info->mode == VIDEO_MODE)
decon_reg_set_linecnt_op_threshold(lcd_info->yres - 1);
decon_reg_set_clkval(0);
decon_reg_set_freerun_mode(1);
decon_reg_direct_on_off(0);
decon_reg_update_standalone();
}
irqreturn_t decon_ext_dsi_irq_handler(int irq, void *dev_data)
{
struct decon_device *decon = dev_data;
ktime_t timestamp = ktime_get();
u32 irq_sts_reg;
u32 wb_irq_sts_reg;
spin_lock(&decon->slock);
irq_sts_reg = decon_read(decon->id, VIDINTCON1);
wb_irq_sts_reg = decon_read(decon->id, VIDINTCON3);
if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
/* VSYNC interrupt, accept it */
decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FRAME);
decon->vsync_info.timestamp = timestamp;
wake_up_interruptible_all(&decon->vsync_info.wait);
}
if (irq_sts_reg & VIDINTCON1_INT_FIFO) {
decon_err("DECON-ext FIFO underrun\n");
decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FIFO);
}
if (irq_sts_reg & VIDINTCON1_INT_I80) {
decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_I80);
wake_up_interruptible_all(&decon->wait_frmdone);
}
#if 0
if (wb_irq_sts_reg & VIDINTCON3_WB_FRAME_DONE) {
decon_dbg("write-back frame done\n");
DISP_SS_EVENT_LOG(DISP_EVT_WB_FRAME_DONE, &decon->sd, ktime_set(0, 0));
decon_write_mask(decon->id, VIDINTCON3, ~0, VIDINTCON3_WB_FRAME_DONE);
atomic_set(&decon->wb_done, STATE_DONE);
wake_up_interruptible_all(&decon->wait_frmdone);
decon_reg_per_frame_off(decon->id);
decon_reg_update_standalone(decon->id);
decon_reg_wb_swtrigger(decon->id);
decon_reg_wait_stop_status_timeout(decon->id, 20 * 1000);
}
#endif
spin_unlock(&decon->slock);
return IRQ_HANDLED;
}
/* enable each window */
void decon_reg_activate_window(u32 index)
{
decon_write_mask(WINCON(index), ~0, WINCONx_ENWIN);
decon_reg_update_standalone();
}
static void decon_activate_window_dma(struct decon_device *decon, unsigned int index)
{
decon_reg_direct_on_off(decon->id, 1);
decon_reg_update_standalone(decon->id);
}
