int decon_reg_stop(struct decon_psr_info *psr)
{
	int ret = 0;

	if ((psr->psr_mode == S3C_FB_MIPI_COMMAND_MODE) &&
			(psr->trig_mode == DECON_HW_TRIG)) {
		decon_reg_set_trigger(psr->trig_mode, DECON_TRIG_DISABLE);
	}

	/* timeout : 200ms */
	ret = decon_reg_wait_linecnt_is_zero_timeout(2000 * 100);
	if (ret)
		goto err;

	if (psr->psr_mode == S3C_FB_MIPI_COMMAND_MODE)
		decon_reg_direct_on_off(0);
	else
		decon_reg_per_frame_off();

	/* timeout : 20ms */
	ret = decon_reg_wait_stop_status_timeout(2000 * 10);
	if (ret)
		goto err;

err:
	ret = decon_reg_reset();

	return ret;
}
irqreturn_t decon_ext_dsi_irq_handler(int irq, void *dev_data)
{
	struct decon_device *decon = dev_data;
	ktime_t timestamp = ktime_get();
	u32 irq_sts_reg;
	u32 wb_irq_sts_reg;

	spin_lock(&decon->slock);

	irq_sts_reg = decon_read(decon->id, VIDINTCON1);
	wb_irq_sts_reg = decon_read(decon->id, VIDINTCON3);
	if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
		/* VSYNC interrupt, accept it */
		decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FRAME);
		decon->vsync_info.timestamp = timestamp;
		wake_up_interruptible_all(&decon->vsync_info.wait);
	}
	if (irq_sts_reg & VIDINTCON1_INT_FIFO) {
		decon_err("DECON-ext FIFO underrun\n");
		decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FIFO);
	}
	if (irq_sts_reg & VIDINTCON1_INT_I80) {
		decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_I80);
		wake_up_interruptible_all(&decon->wait_frmdone);
	}
#if 0 
	if (wb_irq_sts_reg & VIDINTCON3_WB_FRAME_DONE) {
		decon_dbg("write-back frame done\n");
		DISP_SS_EVENT_LOG(DISP_EVT_WB_FRAME_DONE, &decon->sd, ktime_set(0, 0));
		decon_write_mask(decon->id, VIDINTCON3, ~0, VIDINTCON3_WB_FRAME_DONE);
		atomic_set(&decon->wb_done, STATE_DONE);
		wake_up_interruptible_all(&decon->wait_frmdone);
		decon_reg_per_frame_off(decon->id);
		decon_reg_update_standalone(decon->id);
		decon_reg_wb_swtrigger(decon->id);
		decon_reg_wait_stop_status_timeout(decon->id, 20 * 1000);
	}
#endif
	spin_unlock(&decon->slock);
	return IRQ_HANDLED;
}