static void sca_init_port(port_t *port) { card_t *card = port->card; u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port); int transmit, i; port->rxin = 0; port->txin = 0; port->txlast = 0; for (transmit = 0; transmit < 2; transmit++) { u16 buffs = transmit ? card->tx_ring_buffers : card->rx_ring_buffers; for (i = 0; i < buffs; i++) { pkt_desc __iomem *desc = desc_address(port, i, transmit); u16 chain_off = desc_offset(port, i + 1, transmit); u32 buff_off = buffer_offset(port, i, transmit); writel(chain_off, &desc->cp); writel(buff_off, &desc->bp); writew(0, &desc->len); writeb(0, &desc->stat); } } /* DMA disable - to halt state */ sca_out(0, DSR_RX(port->chan), card); sca_out(0, DSR_TX(port->chan), card); /* software ABORT - to initial state */ sca_out(DCR_ABORT, DCR_RX(port->chan), card); sca_out(DCR_ABORT, DCR_TX(port->chan), card); /* current desc addr */ sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card); sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0), dmac_rx + EDAL, card); sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card); sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card); /* clear frame end interrupt counter */ sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card); sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card); /* Receive */ sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */ sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */ sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */ sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */ /* Transmit */ sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */ sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */ sca_set_carrier(port); netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT); }
static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, int transmit) { #ifdef PAGE0_ALWAYS_MAPPED return (pkt_desc __iomem *)(win0base(port_to_card(port)) + desc_offset(port, desc, transmit)); #else return (pkt_desc __iomem *)(winbase(port_to_card(port)) + desc_offset(port, desc, transmit)); #endif }
/* Transmit DMA interrupt service */ static inline void sca_tx_intr(port_t *port) { struct net_device *dev = port_to_dev(port); u16 dmac = get_dmac_tx(port); card_t* card = port_to_card(port); u8 stat; spin_lock(&port->lock); stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */ /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_TX(phy_node(port)), card); while (1) { pkt_desc __iomem *desc; u32 desc_off = desc_offset(port, port->txlast, 1); u32 cda = sca_inw(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; /* Transmitter is/will_be sending this frame */ desc = desc_address(port, port->txlast, 1); dev->stats.tx_packets++; dev->stats.tx_bytes += readw(&desc->len); writeb(0, &desc->stat); /* Free descriptor */ port->txlast = next_desc(port, port->txlast, 1); } netif_wake_queue(dev); spin_unlock(&port->lock); }
/* Receive DMA service */ static inline int sca_rx_done(port_t *port, int budget) { struct net_device *dev = port->netdev; u16 dmac = get_dmac_rx(port); card_t *card = port->card; u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */ int received = 0; /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_RX(port->chan), card); if (stat & DSR_BOF) /* Dropped one or more frames */ dev->stats.rx_over_errors++; while (received < budget) { u32 desc_off = desc_offset(port, port->rxin, 0); pkt_desc __iomem *desc; u32 cda = sca_inl(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; /* No frame received */ desc = desc_address(port, port->rxin, 0); stat = readb(&desc->stat); if (!(stat & ST_RX_EOM)) port->rxpart = 1; /* partial frame received */ else if ((stat & ST_ERROR_MASK) || port->rxpart) { dev->stats.rx_errors++; if (stat & ST_RX_OVERRUN) dev->stats.rx_fifo_errors++; else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | ST_RX_RESBIT)) || port->rxpart) dev->stats.rx_frame_errors++; else if (stat & ST_RX_CRC) dev->stats.rx_crc_errors++; if (stat & ST_RX_EOM) port->rxpart = 0; /* received last fragment */ } else { sca_rx(card, port, desc, port->rxin); received++; } /* Set new error descriptor address */ sca_outl(desc_off, dmac + EDAL, card); port->rxin = (port->rxin + 1) % card->rx_ring_buffers; } /* make sure RX DMA is enabled */ sca_out(DSR_DE, DSR_RX(port->chan), card); return received; }
static inline void sca_rx_intr(port_t *port) { struct net_device *dev = port_to_dev(port); u16 dmac = get_dmac_rx(port); card_t *card = port_to_card(port); u8 stat = sca_in(DSR_RX(phy_node(port)), card); sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_RX(phy_node(port)), card); if (stat & DSR_BOF) dev->stats.rx_over_errors++; while (1) { u32 desc_off = desc_offset(port, port->rxin, 0); pkt_desc __iomem *desc; u32 cda = sca_inw(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; desc = desc_address(port, port->rxin, 0); stat = readb(&desc->stat); if (!(stat & ST_RX_EOM)) port->rxpart = 1; else if ((stat & ST_ERROR_MASK) || port->rxpart) { dev->stats.rx_errors++; if (stat & ST_RX_OVERRUN) dev->stats.rx_fifo_errors++; else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | ST_RX_RESBIT)) || port->rxpart) dev->stats.rx_frame_errors++; else if (stat & ST_RX_CRC) dev->stats.rx_crc_errors++; if (stat & ST_RX_EOM) port->rxpart = 0; } else sca_rx(card, port, desc, port->rxin); sca_outw(desc_off, dmac + EDAL, card); port->rxin = next_desc(port, port->rxin, 0); } sca_out(DSR_DE, DSR_RX(phy_node(port)), card); }
/* Receive DMA interrupt service */ static inline void sca_rx_intr(port_t *port) { u16 dmac = get_dmac_rx(port); card_t *card = port_to_card(port); u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ struct net_device_stats *stats = hdlc_stats(port_to_dev(port)); /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_RX(phy_node(port)), card); if (stat & DSR_BOF) stats->rx_over_errors++; /* Dropped one or more frames */ while (1) { u32 desc_off = desc_offset(port, port->rxin, 0); pkt_desc __iomem *desc; u32 cda = sca_ina(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; /* No frame received */ desc = desc_address(port, port->rxin, 0); stat = readb(&desc->stat); if (!(stat & ST_RX_EOM)) port->rxpart = 1; /* partial frame received */ else if ((stat & ST_ERROR_MASK) || port->rxpart) { stats->rx_errors++; if (stat & ST_RX_OVERRUN) stats->rx_fifo_errors++; else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | ST_RX_RESBIT)) || port->rxpart) stats->rx_frame_errors++; else if (stat & ST_RX_CRC) stats->rx_crc_errors++; if (stat & ST_RX_EOM) port->rxpart = 0; /* received last fragment */ } else sca_rx(card, port, desc, port->rxin); /* Set new error descriptor address */ sca_outa(desc_off, dmac + EDAL, card); port->rxin = next_desc(port, port->rxin, 0); } /* make sure RX DMA is enabled */ sca_out(DSR_DE, DSR_RX(phy_node(port)), card); }
int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt) { struct sk_buff *skb; struct htt_cmd *cmd; struct htt_rx_ring_setup_ring *ring; const int num_rx_ring = 1; u16 flags; u32 fw_idx; int len; int ret; /* * the HW expects the buffer to be an integral number of 4-byte * "words" */ BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr) + (sizeof(*ring) * num_rx_ring); skb = ath10k_htc_alloc_skb(len); if (!skb) return -ENOMEM; skb_put(skb, len); cmd = (struct htt_cmd *)skb->data; ring = &cmd->rx_setup.rings[0]; cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; cmd->rx_setup.hdr.num_rings = 1; /* FIXME: do we need all of this? */ flags = 0; flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; flags |= HTT_RX_RING_FLAGS_PPDU_START; flags |= HTT_RX_RING_FLAGS_PPDU_END; flags |= HTT_RX_RING_FLAGS_MPDU_START; flags |= HTT_RX_RING_FLAGS_MPDU_END; flags |= HTT_RX_RING_FLAGS_MSDU_START; flags |= HTT_RX_RING_FLAGS_MSDU_END; flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; flags |= HTT_RX_RING_FLAGS_FRAG_INFO; flags |= HTT_RX_RING_FLAGS_UNICAST_RX; flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; flags |= HTT_RX_RING_FLAGS_CTRL_RX; flags |= HTT_RX_RING_FLAGS_MGMT_RX; flags |= HTT_RX_RING_FLAGS_NULL_RX; flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); ring->fw_idx_shadow_reg_paddr = __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); ring->flags = __cpu_to_le16(flags); ring->fw_idx_init_val = __cpu_to_le16(fw_idx); #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); #undef desc_offset ATH10K_SKB_CB(skb)->htt.is_conf = true; ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); if (ret) { dev_kfree_skb_any(skb); return ret; } return 0; }
static void sca_init_port(port_t *port) { card_t *card = port_to_card(port); int transmit, i; port->rxin = 0; port->txin = 0; port->txlast = 0; #ifndef PAGE0_ALWAYS_MAPPED openwin(card, 0); #endif for (transmit = 0; transmit < 2; transmit++) { u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); u16 buffs = transmit ? card->tx_ring_buffers : card->rx_ring_buffers; for (i = 0; i < buffs; i++) { pkt_desc __iomem *desc = desc_address(port, i, transmit); u16 chain_off = desc_offset(port, i + 1, transmit); u32 buff_off = buffer_offset(port, i, transmit); writew(chain_off, &desc->cp); writel(buff_off, &desc->bp); writew(0, &desc->len); writeb(0, &desc->stat); } /* DMA disable - to halt state */ sca_out(0, transmit ? DSR_TX(phy_node(port)) : DSR_RX(phy_node(port)), card); /* software ABORT - to initial state */ sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : DCR_RX(phy_node(port)), card); /* current desc addr */ sca_out(0, dmac + CPB, card); /* pointer base */ sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card); if (!transmit) sca_outw(desc_offset(port, buffs - 1, transmit), dmac + EDAL, card); else sca_outw(desc_offset(port, 0, transmit), dmac + EDAL, card); /* clear frame end interrupt counter */ sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : DCR_RX(phy_node(port)), card); if (!transmit) { /* Receive */ /* set buffer length */ sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); /* Chain mode, Multi-frame */ sca_out(0x14, DMR_RX(phy_node(port)), card); sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), card); /* DMA enable */ sca_out(DSR_DE, DSR_RX(phy_node(port)), card); } else { /* Transmit */ /* Chain mode, Multi-frame */ sca_out(0x14, DMR_TX(phy_node(port)), card); /* enable underflow interrupts */ sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); } } sca_set_carrier(port); }
static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, int transmit) { return (pkt_desc __iomem *)(port->card->rambase + desc_offset(port, desc, transmit)); }
static void sca_init_port(port_t *port) { card_t *card = port_to_card(port); int transmit, i; port->rxin = 0; port->txin = 0; port->txlast = 0; #ifndef PAGE0_ALWAYS_MAPPED openwin(card, 0); #endif for (transmit = 0; transmit < 2; transmit++) { u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); u16 buffs = transmit ? card->tx_ring_buffers : card->rx_ring_buffers; for (i = 0; i < buffs; i++) { pkt_desc __iomem *desc = desc_address(port, i, transmit); u16 chain_off = desc_offset(port, i + 1, transmit); u32 buff_off = buffer_offset(port, i, transmit); writew(chain_off, &desc->cp); writel(buff_off, &desc->bp); writew(0, &desc->len); writeb(0, &desc->stat); } sca_out(0, transmit ? DSR_TX(phy_node(port)) : DSR_RX(phy_node(port)), card); sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : DCR_RX(phy_node(port)), card); sca_out(0, dmac + CPB, card); sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card); if (!transmit) sca_outw(desc_offset(port, buffs - 1, transmit), dmac + EDAL, card); else sca_outw(desc_offset(port, 0, transmit), dmac + EDAL, card); sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : DCR_RX(phy_node(port)), card); if (!transmit) { sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); sca_out(0x14, DMR_RX(phy_node(port)), card); sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), card); sca_out(DSR_DE, DSR_RX(phy_node(port)), card); } else { sca_out(0x14, DMR_TX(phy_node(port)), card); sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); } } sca_set_carrier(port); }