char mcp_read_status(){
selectChip();
SPI_MasterTransmit(MCP_READ_STATUS);
SPI_MasterTransmit(0xff);
deselectChip();
return SPI_MasterRead();
}
static enum Status getRawCounts(struct LIS3DSH_rawData* rawData)
{
uint32_t xmit = 0;
const uint8_t cmd = READ_REGISTER_CMD | OUT_X_L_ADDR;
selectChip();
enum Status status = spi_write(&LIS3DSH_BUS, (uint8_t*) &cmd, sizeof(cmd), &xmit);
uint8_t data[6] = { 0 };
if (STATUS_OK == status)
{
status = spi_read(&LIS3DSH_BUS, data, sizeof(data), &xmit);
}
deselectChip();
if (STATUS_OK == status)
{
rawData->x = ((int16_t) ((((uint16_t) data[1]) << 8) | data[0]));
rawData->y = ((int16_t) ((((uint16_t) data[3]) << 8) | data[2]));
rawData->z = ((int16_t) ((((uint16_t) data[5]) << 8) | data[4]));
}
else
{
memset(rawData, 0, sizeof(*rawData));
}
return status;
}
void mcp_write(char reg, char byte){
selectChip();
SPI_MasterTransmit(MCP_WRITE);
SPI_MasterTransmit(reg);
SPI_MasterTransmit(byte);
deselectChip();
}
void mcp_bit_modify_instruction(char reg, char mask, char data){
selectChip();
SPI_MasterTransmit(MCP_BITMOD);
SPI_MasterTransmit(reg);
SPI_MasterTransmit(mask);
SPI_MasterTransmit(data);
deselectChip();
}
char mcp_read(char reg){
selectChip();
SPI_MasterTransmit(MCP_READ);
SPI_MasterTransmit(reg);
SPI_MasterTransmit(0xFF);
deselectChip();
return SPI_MasterRead();
}
void mcp_init(){
deselectChip();
SPI_MasterTransmit(MCP_RESET);
//setLoopbackOperationalMode();
setOperationModeNormal();
mcp_write(MCP_CANINTE, MCP_RX_INT);
mcp_bit_modify_instruction(MCP_RXB0CTRL, 0b01100000, 0xFF);
}
void NMCP23S17::writeRegister(uint8_t reg, uint8_t data)
{
uint8_t control_byte = getSPIControlByte(WRITE_CMD);
selectChip();
SPI.transfer(control_byte);
SPI.transfer(reg);
SPI.transfer(data);
deselectChip();
}
enum Status LIS3DSH_enableFIFO(void)
{
enum Status status = reserveBus();
uint32_t xmit = 0;
if (STATUS_OK == status)
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) enableFIFO, sizeof(enableFIFO), &xmit);
deselectChip();
if (STATUS_OK == status)
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) setFIFOMode, sizeof(setFIFOMode), &xmit);
deselectChip();
}
releaseBus();
}
return status;
}
uint8_t NMCP23S17::readRegister(uint8_t reg)
{
uint8_t control_byte = getSPIControlByte(READ_CMD);
uint8_t value = 0;
selectChip();
SPI.transfer(control_byte);
SPI.transfer(reg);
value = SPI.transfer(0x00);
deselectChip();
return value;
}
enum Status LIS3DSH_disableFIFO(void)
{
uint32_t xmit = 0;
enum Status status = reserveBus();
if (STATUS_OK == status)
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) disableFIFO, sizeof(disableFIFO), &xmit);
deselectChip();
releaseBus();
}
return status;
}
void mcp_request_to_send(int reg){
char rtsreg = 0x00;
switch(reg){
case 0:
rtsreg = MCP_RTS_TX0;
break;
case 1:
rtsreg = MCP_RTS_TX1;
break;
case 2:
rtsreg = MCP_RTS_TX2;
break;
default:
rtsreg = MCP_RTS_ALL;
}
selectChip();
SPI_MasterTransmit(rtsreg);
deselectChip();
}
enum Status LIS3DSH_readFIFO(struct LIS3DSH_rawData* data, uint32_t capacity, uint32_t* valuesCount)
{
uint32_t xmit = 0;
uint32_t readCount = 0;
enum Status status = reserveBus();
if (STATUS_OK == status)
{
uint8_t fifoSrc = 0;
{
const uint8_t cmd = READ_REGISTER_CMD | FIFO_SRC_REG;
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) &cmd, sizeof(cmd), &xmit);
if (STATUS_OK == status)
{
status = spi_read(&LIS3DSH_BUS, &fifoSrc, sizeof(fifoSrc), &xmit);
}
deselectChip();
}
uint32_t samplesCount = (fifoSrc & FIFO_SRC_SAMPLES_MASK);
while ((STATUS_OK == status) && samplesCount && (readCount < capacity))
{
status = getRawCounts(&data[readCount]);
readCount ++;
samplesCount --;
}
releaseBus();
}
*valuesCount = readCount;
return status;
}
enum Status LIS3DSH_getRawCounts(uint8_t* dataStatus, struct LIS3DSH_rawData* rawData)
{
enum Status status = reserveBus();
if (STATUS_OK == status)
{
uint32_t xmit = 0;
const uint8_t cmd = READ_REGISTER_CMD | STATUS;
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) &cmd, sizeof(cmd), &xmit);
uint8_t data[7] = { 0 };
if (STATUS_OK == status)
{
status = spi_read(&LIS3DSH_BUS, data, sizeof(data), &xmit);
}
deselectChip();
releaseBus();
if (STATUS_OK == status)
{
*dataStatus = data[0];
rawData->x = ((int16_t) ((((uint16_t) data[2]) << 8) | data[1]));
rawData->y = ((int16_t) ((((uint16_t) data[4]) << 8) | data[3]));
rawData->z = ((int16_t) ((((uint16_t) data[6]) << 8) | data[5]));
}
else
{
*dataStatus = 0;
memset(rawData, 0, sizeof(*rawData));
}
}
return status;
}
enum Status LIS3DSH_getChipId(uint32_t* expectedId, uint32_t* actualId)
{
*expectedId = 0x37;
*actualId = 0xff;
enum Status status = reserveBus();
if (STATUS_OK != status)
{
return status;
}
uint32_t xmit = 0;
const uint8_t cmd = READ_REGISTER_CMD | MULTIPLE_SELECT | REG_INFO1;
uint8_t rawData[3] = { 0 };
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) &cmd, sizeof(cmd), &xmit);
if (STATUS_OK == status)
{
status = spi_read(&LIS3DSH_BUS, rawData, sizeof(rawData), &xmit);
}
deselectChip();
releaseBus();
if (STATUS_OK == status)
{
*actualId =
(((uint32_t) rawData[0]) << 16) |
(((uint32_t) rawData[1]) << 8) |
((uint32_t) rawData[2]);
}
return status;
}
enum Status LIS3DSH_initialize(void)
{
bsp_initializeOutputPin(LIS3DSH_CHIP_SELECT);
enum Status status = reserveBus();
uint32_t xmit = 0;
if (STATUS_OK == status)
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) resetSequence, sizeof(resetSequence), &xmit);
deselectChip();
}
fx3_suspendTask(20); // wake-up time: 10 ms
if (STATUS_OK == status);
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) enableMultibyteAutoincrement, sizeof(enableMultibyteAutoincrement), &xmit);
deselectChip();
bsp_delay(8);
}
if (STATUS_OK == status);
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) enable2gScale, sizeof(enable2gScale), &xmit);
deselectChip();
bsp_delay(8);
}
if (STATUS_OK == status);
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) setSamplingRateAndEnable, sizeof(setSamplingRateAndEnable), &xmit);
deselectChip();
}
if (STATUS_OK == status);
{
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) enableInterrupts, sizeof(enableInterrupts), &xmit);
deselectChip();
}
/*
* check settings
*/
if (STATUS_OK == status)
{
const uint8_t cmd = READ_REGISTER_CMD | CTRL_REG4_ADDR;
selectChip();
status = spi_write(&LIS3DSH_BUS, (uint8_t*) &cmd, sizeof(cmd), &xmit);
uint8_t configuredRegisters[7] = { 0 };
if (STATUS_OK == status)
{
status = spi_read(&LIS3DSH_BUS, configuredRegisters, sizeof(configuredRegisters), &xmit);
if (setSamplingRateAndEnable[1] != configuredRegisters[0])
{
status = STATUS_HARDWARE_CONFIGURATION_FAILED;
}
}
deselectChip();
}
releaseBus();
if (STATUS_OK == status)
{
fx3_suspendTask(10); // settle time 1/ODR
}
return status;
}
void mcp_reset(){
selectChip();
SPI_MasterTransmit(MCP_RESET);
deselectChip();
}
static inline void releaseBus(void)
{
deselectChip(); // just in case
spi_releaseBus(&LIS3DSH_BUS);
}
