static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result)
{
int i;
device_t dev;
dev = dev_find_slot_on_smbus(1, 0x54 | bank);
if (dev == 0) {
printk(BIOS_WARNING, "EEPROM not found\n");
memcpy(result, "*INVALID*", sizeof ("*INVALID*"));
return;
}
for (i = 0; i < len; i++) {
int t;
int j;
/* After a register write AT24RF08C (which we issued in init function) sometimes stops responding.
Retry several times in case of failure.
*/
for (j = 0; j < 100; j++) {
t = smbus_read_byte(dev, start + i);
if (t >= 0)
break;
}
if (t < 0x20 || t > 0x7f) {
memcpy(result, "*INVALID*", sizeof ("*INVALID*"));
return;
}
result[i] = t;
}
}
void smbios_mainboard_set_uuid(u8 *uuid)
{
static char result[16];
unsigned i;
static int already_read;
device_t dev;
const int remap[16] = {
/* UUID byteswap. */
3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15
};
if (already_read) {
memcpy (uuid, result, 16);
return;
}
memset (result, 0, sizeof (result));
dev = dev_find_slot_on_smbus(1, 0x56);
if (dev == 0) {
printk(BIOS_WARNING, "eeprom not found\n");
already_read = 1;
memset (uuid, 0, 16);
return;
}
for (i = 0; i < 16; i++) {
int t;
int j;
/* After a register write AT24RF08C (which we issued in init function) sometimes stops responding.
Retry several times in case of failure.
*/
for (j = 0; j < 100; j++) {
t = smbus_read_byte(dev, 0x12 + i);
if (t >= 0)
break;
}
if (t < 0) {
memset (result, 0, sizeof (result));
break;
}
result[remap[i]] = t;
}
already_read = 1;
memcpy (uuid, result, 16);
}
static void init(struct device *dev)
{
unsigned int i;
u32 chksum = 0;
char block[20];
msr_t reset;
device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
if (eeprom_dev == 0) {
printk(BIOS_WARNING, "eeprom not found\n");
return;
}
/* turn off all leds except led_ini */
outb(0x02, 0x5a); /* bit0 - led_run */
/* bit1 - led_ini */
/* bit2 - led_err */
/* bit3-bit7 - write has no effect */
outb(0x00, 0x49); /* bit0-bit6 - led_7-led_1 */
/* bit7 - write has no effect */
/* read the whole block and check if checksum is okay */
for (i = 0; i < 20; i++) {
block[i] = smbus_read_byte(eeprom_dev, i);
chksum += block[i];
}
if (chksum != 0) {
printk(BIOS_WARNING, "wrong checksum: 0x%0x\n", chksum);
}
hw_rev = block[5];
printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev);
/* Reset MFGPT7 (standby power domain) - this is done via
* an undocumented register */
reset = rdmsr(0x5140002b);
reset.lo |= 1 << 7;
wrmsr(0x5140002b, reset);
}
static enum cb_err cubieboard_setup_power(void)
{
enum cb_err err;
const struct device * pmu;
const struct drivers_xpowers_axp209_config *cfg;
/* Find the AXP209 in devicetree */
pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR);
if (!pmu) {
printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n");
return CB_ERR;
}
cfg = pmu->chip_info;
/* Mux TWI0 pins */
gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC);
/* Enable TWI0 */
a1x_periph_clock_enable(A1X_CLKEN_TWI0);
a1x_twi_init(AXP209_BUS, 400000);
if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) {
printk(BIOS_ERR, "PMU initialization failed\n");
return err;
}
if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) {
printk(BIOS_WARNING, "Power setup incomplete: "
"CPU may hang when increasing clock\n");
return err;
}
printk(BIOS_SPEW, "VDD CPU (DCDC2): %imv\n", cfg->dcdc2_voltage_mv);
printk(BIOS_SPEW, "VDD DLL (DCDC3): %imv\n", cfg->dcdc3_voltage_mv);
printk(BIOS_SPEW, "AVCC (LDO2) : %imv\n", cfg->ldo2_voltage_mv);
printk(BIOS_SPEW, "CSI1-IO (LDO4) : %imv\n", cfg->ldo4_voltage_mv);
printk(BIOS_SPEW, "(LDO3) : %imv\n", cfg->ldo3_voltage_mv);
return CB_SUCCESS;
}
static void nic_init(struct device *dev)
{
u32 dword, old, mac_h = 0, mac_l = 0;
int eeprom_valid = 0;
struct southbridge_nvidia_ck804_config *conf;
static u32 nic_index = 0;
u8 *base;
struct resource *res;
res = find_resource(dev, 0x10);
base = res2mmio(res, 0, 0);
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
write32(base + NvRegPhyInterface, PHY_RGMII);
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
dword |= 0xf;
if (old != dword)
pci_write_config32(dev, 0x30, dword);
conf = dev->chip_info;
if (conf->mac_eeprom_smbus != 0) {
/* Read MAC address from EEPROM at first. */
struct device *dev_eeprom;
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
conf->mac_eeprom_addr);
if (dev_eeprom) {
/* If that is valid we will use that. */
unsigned char dat[6];
int i, status;
for (i = 0; i < 6; i++) {
status = smbus_read_byte(dev_eeprom, i);
if (status < 0)
break;
dat[i] = status & 0xff;
}
if (status >= 0) {
mac_l = 0;
for (i = 3; i >= 0; i--) {
mac_l <<= 8;
mac_l += dat[i];
}
if (mac_l != 0xffffffff) {
mac_l += nic_index;
mac_h = 0;
for (i = 5; i >= 4; i--) {
mac_h <<= 8;
mac_h += dat[i];
}
eeprom_valid = 1;
}
}
}
}
/* If that is invalid we will read that from romstrap. */
if (!eeprom_valid) {
u32 *mac_pos;
mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */
mac_l = read32(mac_pos) + nic_index;
mac_h = read32(mac_pos + 1);
}
#if 1
/* Set that into NIC MMIO. */
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
write32(base + NvRegMacAddrA, mac_l);
write32(base + NvRegMacAddrB, mac_h);
#else
/* Set that into NIC. */
pci_write_config32(dev, 0xa8, mac_l);
pci_write_config32(dev, 0xac, mac_h);
#endif
nic_index++;
}
static void nic_init(struct device *dev)
{
u8 *base;
u32 mac_h = 0, mac_l = 0;
int eeprom_valid = 0;
struct southbridge_nvidia_mcp55_config *conf;
static u32 nic_index = 0;
struct resource *res;
res = find_resource(dev, 0x10);
if (!res)
return;
base = res2mmio(res, 0, 0);
phy_detect(base);
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
write32(base + NvRegPhyInterface, PHY_RGMII);
conf = dev->chip_info;
if (conf->mac_eeprom_smbus != 0) {
// read MAC address from EEPROM at first
struct device *dev_eeprom;
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
if(dev_eeprom) {
// if that is valid we will use that
unsigned char dat[6];
int status;
int i;
for(i=0;i<6;i++) {
status = smbus_read_byte(dev_eeprom, i);
if(status < 0) break;
dat[i] = status & 0xff;
}
if(status >= 0) {
mac_l = 0;
for(i=3;i>=0;i--) {
mac_l <<= 8;
mac_l += dat[i];
}
if(mac_l != 0xffffffff) {
mac_l += nic_index;
mac_h = 0;
for(i=5;i>=4;i--) {
mac_h <<= 8;
mac_h += dat[i];
}
eeprom_valid = 1;
}
}
}
}
// if that is invalid we will read that from romstrap
if(!eeprom_valid) {
u32 *mac_pos;
mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld
mac_l = read32(mac_pos) + nic_index; // overflow?
mac_h = read32(mac_pos + 1);
}
#if 1
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
write32(base + NvRegMacAddrA, mac_l);
write32(base + NvRegMacAddrB, mac_h);
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);
pci_write_config32(dev, 0xac, mac_h);
#endif
nic_index++;
}