static int ohci_usb_probe(struct udevice *dev)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
struct ohci_sunxi_priv *priv = dev_get_priv(dev);
struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
bus_priv->companion = true;
/*
* This should go away once we've moved to the driver model for
* clocks resp. phys.
*/
if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) {
priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
priv->phy_index = 1;
} else {
priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1;
priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK;
priv->phy_index = 2;
}
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
#endif
sunxi_usb_phy_init(priv->phy_index);
sunxi_usb_phy_power_on(priv->phy_index);
return ohci_register(dev, regs);
}
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->emio = 0;
priv->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
/* use non-removeable as sdcard and emmc as judgement */
if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
host->dev_index = 0;
else
host->dev_index = 1;
priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"fifo-depth", 0);
if (priv->fifo_depth < 0)
return -EINVAL;
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
"fifo-mode");
if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
"clock-freq-min-max", priv->minmax, 2))
return -EINVAL;
#endif
return 0;
}
static int macb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
pdata->iobase = dev_get_addr(dev);
return 0;
}
static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
plat->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int atmel_spi_probe(struct udevice *bus)
{
struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
struct atmel_spi_priv *priv = dev_get_priv(bus);
int i, ret;
ret = atmel_spi_enable_clk(bus);
if (ret)
return ret;
bus_plat->regs = (struct at91_spi *)dev_get_addr(bus);
ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
ARRAY_SIZE(priv->cs_gpios), 0);
if (ret < 0) {
error("Can't get %s gpios! Error: %d", bus->name, ret);
return ret;
}
for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
dm_gpio_set_dir_flags(&priv->cs_gpios[i],
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
return 0;
}
static int ehci_usb_probe(struct udevice *dev)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct usb_platdata *plat = dev_get_platdata(dev);
struct ehci_sunxi_priv *priv = dev_get_priv(dev);
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
struct ehci_hcor *hcor;
/*
* This should go away once we've moved to the driver model for
* clocks resp. phys.
*/
priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
#ifdef CONFIG_MACH_SUN8I_H3
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
priv->ahb_gate_mask <<= priv->phy_index - 1;
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
#endif
sunxi_usb_phy_init(priv->phy_index);
sunxi_usb_phy_power_on(priv->phy_index);
hcor = (struct ehci_hcor *)((uint32_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
}
static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
struct xenon_sdhci_priv *priv = dev_get_priv(dev);
const char *name;
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
if (of_device_is_compatible(dev, "marvell,armada-3700-sdhci"))
priv->pad_ctrl_reg = (void *)dev_get_addr_index(dev, 1);
name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);
if (name) {
if (0 == strncmp(name, "sd", 2)) {
priv->pad_type = SOC_PAD_SD;
} else if (0 == strncmp(name, "fixed-1-8v", 10)) {
priv->pad_type = SOC_PAD_FIXED_1_8V;
} else {
printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
return -EINVAL;
}
}
return 0;
}
static int fecmxc_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct fec_priv *priv = dev_get_priv(dev);
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
/* TODO
* Need to get the reset-gpio and related properties from DT
* and implemet the enet reset code on .probe call
*/
return 0;
}
static int uniphier_gpio_probe(struct udevice *dev)
{
struct uniphier_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
fdt_addr_t addr;
unsigned int tmp;
addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = devm_ioremap(dev, addr, SZ_8);
if (!priv->base)
return -ENOMEM;
uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK;
tmp = (addr & 0xfff);
/* Unfortunately, there is a register hole at offset 0x90-0x9f. */
if (tmp > 0x90)
tmp -= 0x10;
snprintf(priv->bank_name, sizeof(priv->bank_name) - 1,
"port%d-", (tmp - 8) / 8);
uc_priv->bank_name = priv->bank_name;
return 0;
}
static int uniphier_serial_probe(struct udevice *dev)
{
DECLARE_GLOBAL_DATA_PTR;
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial __iomem *port;
fdt_addr_t base;
u32 tmp;
base = dev_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
port = devm_ioremap(dev, base, SZ_64);
if (!port)
return -ENOMEM;
priv->membase = port;
priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"clock-frequency", 0);
tmp = readl(&port->lcr_mcr);
tmp &= ~LCR_MASK;
tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
writel(tmp, &port->lcr_mcr);
return 0;
}
static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
0x10000);
emaclite->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,tx-ping-pong", 0);
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
return 0;
}
static int ehci_usb_probe(struct udevice *dev)
{
struct usb_platdata *plat = dev_get_platdata(dev);
struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev);
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
priv->ehci = ehci;
priv->portnr = dev->seq;
priv->init_type = plat->init_type;
ret = ehci_mx6_common_init(ehci, priv->portnr);
if (ret)
return ret;
board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1);
if (priv->init_type == USB_INIT_HOST) {
setbits_le32(&ehci->usbmode, CM_HOST);
writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
}
mdelay(10);
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
}
static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
struct rockchip_spi_platdata *plat = bus->platdata;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
int ret;
plat->base = dev_get_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
debug("%s: Could not get clock for %s: %d\n", __func__,
bus->name, ret);
return ret;
}
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
50000000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
plat->activate_delay_us = fdtdec_get_int(blob, node,
"spi-activate-delay", 0);
debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
__func__, (uint)plat->base, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
priv->host = calloc(1, sizeof(struct sdhci_host));
if (priv->host == NULL)
return -1;
priv->host->name = dev->name;
priv->host->ioaddr = (void *)dev_get_addr(dev);
priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,device_id", -1);
priv->bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,mio_bank", -1);
if (fdt_get_property(gd->fdt_blob, dev->of_offset, "no-1-8-v", NULL))
priv->no_1p8 = 1;
else
priv->no_1p8 = 0;
if (fdt_get_property(gd->fdt_blob, dev->of_offset, "mmc-pwrseq", NULL))
priv->pwrseq = true;
return 0;
}
static int ti_edma3_ofdata_to_platdata(struct udevice *dev)
{
struct ti_edma3_priv *priv = dev_get_priv(dev);
priv->base = dev_get_addr(dev);
return 0;
}
static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct pwm_ctlr *)dev_get_addr(dev);
return 0;
}
static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
return 0;
}
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
return 0;
}
static int ehci_usb_probe(struct udevice *dev)
{
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
struct ehci_hcor *hcor;
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
static int altera_timer_ofdata_to_platdata(struct udevice *dev)
{
struct altera_timer_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct altera_timer_regs),
MAP_NOCACHE);
return 0;
}
static int msm_clk_probe(struct udevice *dev)
{
struct msm_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_get_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
return 0;
}
static int altera_spi_ofdata_to_platdata(struct udevice *bus)
{
struct altera_spi_platdata *plat = dev_get_platdata(bus);
plat->regs = map_physmem(dev_get_addr(bus),
sizeof(struct altera_spi_regs),
MAP_NOCACHE);
return 0;
}
static int altera_uart_ofdata_to_platdata(struct udevice *dev)
{
struct altera_uart_platdata *plat = dev_get_platdata(dev);
plat->regs = ioremap(dev_get_addr(dev),
sizeof(struct altera_uart_regs));
plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"clock-frequency", 0);
return 0;
}
static int omap3_spi_probe(struct udevice *dev)
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
priv->regs = (struct mcspi *)dev_get_addr(dev);
priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
MCSPI_PINDIR_D0_IN_D1_OUT);
priv->wordlen = SPI_DEFAULT_WORDLEN;
return 0;
}
static int mvebu_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct mvebu_gpio_priv *priv = dev_get_priv(dev);
priv->regs = (struct mvebu_gpio_regs *)dev_get_addr(dev);
uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK;
priv->name[0] = 'A' + dev->req_seq;
uc_priv->bank_name = priv->name;
return 0;
}
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
/* try Processor Local Bus device first */
addr = dev_get_addr(dev);
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
/* we prefer to use a memory-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
dev->of_offset,
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
return ret;
}
ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
addr = bar;
}
#endif
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 0);
plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
}
return 0;
}
static int altera_pio_ofdata_to_platdata(struct udevice *dev)
{
struct altera_pio_platdata *plat = dev_get_platdata(dev);
plat->regs = ioremap(dev_get_addr(dev),
sizeof(struct altera_pio_regs));
plat->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"altr,gpio-bank-width", 32);
plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
"gpio-bank-name", NULL);
return 0;
}
static int atmel_pinctrl_probe(struct udevice *dev)
{
struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr_base;
dev = dev_get_parent(dev);
addr_base = dev_get_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
plat->reg_base = (struct atmel_pio4_port *)addr_base;
return 0;
}
static int uniphier_clk_probe(struct udevice *dev)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = dev_get_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = devm_ioremap(dev, addr, SZ_4K);
if (!priv->base)
return -ENOMEM;
priv->data = (void *)dev_get_driver_data(dev);
return 0;
}
