static inline bool meson_hdmi_is_compatible(struct meson_dw_hdmi *priv,
enum hdmi_compatible family)
{
enum hdmi_compatible compat = dev_get_driver_data(priv->dev);
return compat == family;
}
static int palmas_ldo_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
struct udevice *parent;
uc_pdata = dev_get_uclass_platdata(dev);
parent = dev_get_parent(dev);
int type = dev_get_driver_data(parent);
uc_pdata->type = REGULATOR_TYPE_LDO;
if (dev->driver_data) {
u8 idx = dev->driver_data - 1;
uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx];
uc_pdata->volt_reg = palmas_ldo_volt[type][idx];
} else {
/* check for ldoln and ldousb cases */
if (!strcmp("ldoln", dev->name)) {
uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9];
uc_pdata->volt_reg = palmas_ldo_volt[type][9];
} else if (!strcmp("ldousb", dev->name)) {
uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10];
uc_pdata->volt_reg = palmas_ldo_volt[type][10];
}
}
return 0;
}
static int imx6_pinctrl_probe(struct udevice *dev)
{
struct imx_pinctrl_soc_info *info =
(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
return imx_pinctrl_probe(dev, info);
}
static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
pdata->iobase = devfdt_get_addr(dev);
pdata->phy_interface = -1;
phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
return -EINVAL;
}
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
priv->rxdes0_edorr_mask = BIT(30);
priv->txdes0_edotr_mask = BIT(30);
} else {
priv->rxdes0_edorr_mask = BIT(15);
priv->txdes0_edotr_mask = BIT(15);
}
return clk_get_bulk(dev, &priv->clks);
}
static int pipe3_phy_probe(struct udevice *dev)
{
fdt_addr_t addr;
fdt_size_t sz;
struct omap_pipe3 *pipe3 = dev_get_priv(dev);
addr = devfdt_get_addr_size_index(dev, 2, &sz);
if (addr == FDT_ADDR_T_NONE) {
pr_err("missing pll ctrl address\n");
return -EINVAL;
}
pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
if (!pipe3->pll_ctrl_base) {
pr_err("unable to remap pll ctrl\n");
return -EINVAL;
}
pipe3->power_reg = get_reg(dev, "syscon-phy-power");
if (!pipe3->power_reg)
return -EINVAL;
pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
if (!pipe3->pll_reset_reg)
return -EINVAL;
pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
return 0;
}
static int stm32_serial_probe(struct udevice *dev)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
struct clk clk;
int ret;
plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
plat->clock_rate = clk_get_rate(&clk);
if (plat->clock_rate < 0) {
clk_disable(&clk);
return plat->clock_rate;
};
_stm32_serial_init(plat->base, plat->uart_info);
return 0;
}
static int periph_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
enum periph_clk_type clk_type;
void *addr;
if (clk->id < PERIPHERAL_ID_MIN)
return -1;
clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
if (clk_type == CLK_PERIPH_AT91RM9200) {
addr = &pmc->pcer;
if (clk->id > PERIPHERAL_ID_MAX)
addr = &pmc->pcer1;
setbits_le32(addr, PERIPHERAL_MASK(clk->id));
} else {
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
setbits_le32(&pmc->pcr,
AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
}
return 0;
}
/**
* We have a top-level GPIO device with no actual GPIOs. It has a child
* device for each Sunxi bank.
*/
static int gpio_sunxi_bind(struct udevice *parent)
{
struct sunxi_gpio_soc_data *soc_data =
(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
struct sunxi_gpio_platdata *plat = parent->platdata;
struct sunxi_gpio_reg *ctlr;
int bank, ret;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
ctlr = (struct sunxi_gpio_reg *)devfdt_get_addr(parent);
for (bank = 0; bank < soc_data->no_banks; bank++) {
struct sunxi_gpio_platdata *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->regs = &ctlr->gpio_bank[bank];
plat->bank_name = gpio_bank_name(soc_data->start + bank);
plat->gpio_count = SUNXI_GPIOS_PER_BANK;
ret = device_bind(parent, parent->driver,
plat->bank_name, plat, -1, &dev);
if (ret)
return ret;
dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
}
static int palmas_ldo_bypass_enable(struct udevice *dev, bool enabled)
{
int type = dev_get_driver_data(dev_get_parent(dev));
struct dm_regulator_uclass_platdata *p;
unsigned int adr;
int reg;
if (type == TPS65917) {
/* bypass available only on LDO1 and LDO2 */
if (dev->driver_data > 2)
return -ENOTSUPP;
} else if (type == TPS659038) {
/* bypass available only on LDO9 */
if (dev->driver_data != 9)
return -ENOTSUPP;
}
p = dev_get_uclass_platdata(dev);
adr = p->ctrl_reg;
reg = pmic_reg_read(dev->parent, adr);
if (reg < 0)
return reg;
if (enabled)
reg |= PALMAS_LDO_BYPASS_EN;
else
reg &= ~PALMAS_LDO_BYPASS_EN;
return pmic_reg_write(dev->parent, adr, reg);
}
static int atmel_serial_enable_clk(struct udevice *dev)
{
struct atmel_serial_priv *priv = dev_get_priv(dev);
struct clk clk;
ulong clk_rate;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return -EINVAL;
if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
ret = clk_enable(&clk);
if (ret)
return ret;
}
clk_rate = clk_get_rate(&clk);
if (!clk_rate)
return -EINVAL;
priv->usart_clk_rate = clk_rate;
clk_free(&clk);
return 0;
}
static int ti_qspi_probe(struct udevice *bus)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
priv->fclk = dev_get_driver_data(bus);
return 0;
}
static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)
{
struct i2c_eeprom *priv = dev_get_priv(dev);
u64 data = dev_get_driver_data(dev);
/* 6 bit -> page size of up to 2^63 (should be sufficient) */
priv->pagewidth = data & 0x3F;
priv->pagesize = (1 << priv->pagewidth);
return 0;
}
static int pfuze100_regulator_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
struct pfuze100_regulator_desc *desc;
switch (dev_get_driver_data(dev_get_parent(dev))) {
case PFUZE100:
desc = se_desc(pfuze100_regulators,
ARRAY_SIZE(pfuze100_regulators),
dev->name);
break;
case PFUZE200:
desc = se_desc(pfuze200_regulators,
ARRAY_SIZE(pfuze200_regulators),
dev->name);
break;
case PFUZE3000:
desc = se_desc(pfuze3000_regulators,
ARRAY_SIZE(pfuze3000_regulators),
dev->name);
break;
default:
debug("Unsupported PFUZE\n");
return -EINVAL;
}
if (!desc) {
debug("Do not support regulator %s\n", dev->name);
return -EINVAL;
}
plat->desc = desc;
uc_pdata = dev_get_uclass_platdata(dev);
uc_pdata->type = desc->type;
if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
if (!strcmp(dev->name, "swbst")) {
uc_pdata->mode = pfuze_swbst_modes;
uc_pdata->mode_count = ARRAY_SIZE(pfuze_swbst_modes);
} else {
uc_pdata->mode = pfuze_sw_modes;
uc_pdata->mode_count = ARRAY_SIZE(pfuze_sw_modes);
}
} else if (uc_pdata->type == REGULATOR_TYPE_LDO) {
uc_pdata->mode = pfuze_ldo_modes;
uc_pdata->mode_count = ARRAY_SIZE(pfuze_ldo_modes);
} else {
uc_pdata->mode = NULL;
uc_pdata->mode_count = 0;
}
return 0;
}
static int at91_i2c_ofdata_to_platdata(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct at91_i2c_bus *bus = dev_get_priv(dev);
int node = dev_of_offset(dev);
bus->regs = (struct at91_i2c_regs *)devfdt_get_addr(dev);
bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev);
bus->clock_frequency = fdtdec_get_int(blob, node,
"clock-frequency", 100000);
return 0;
}
static int tpm_tis_i2c_probe(struct udevice *dev)
{
struct tpm_chip_priv *uc_priv = dev_get_uclass_priv(dev);
struct tpm_chip *chip = dev_get_priv(dev);
chip->chip_type = dev_get_driver_data(dev);
/* TODO: These need to be checked and tuned */
uc_priv->duration_ms[TPM_SHORT] = TIS_SHORT_TIMEOUT_MS;
uc_priv->duration_ms[TPM_MEDIUM] = TIS_LONG_TIMEOUT_MS;
uc_priv->duration_ms[TPM_LONG] = TIS_LONG_TIMEOUT_MS;
uc_priv->retry_time_ms = TPM_TIMEOUT_MS;
return 0;
}
static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
/* reset deassert is done in rcc clr register */
writel(BIT(offset), priv->base + bank + RCC_CL);
else
clrbits_le32(priv->base + bank, BIT(offset));
return 0;
}
static int uniphier_clk_probe(struct udevice *dev)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = dev_get_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = devm_ioremap(dev, addr, SZ_4K);
if (!priv->base)
return -ENOMEM;
priv->data = (void *)dev_get_driver_data(dev);
return 0;
}
int exynos_pinctrl_probe(struct udevice *dev)
{
struct exynos_pinctrl_priv *priv;
fdt_addr_t base;
priv = dev_get_priv(dev);
if (!priv)
return -EINVAL;
base = dev_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = base;
priv->pin_ctrl = (struct samsung_pin_ctrl *)dev_get_driver_data(dev) +
dev->req_seq;
return 0;
}
/**
* k3_sysctrler_probe() - Basic probe
* @dev: corresponding k3 remote processor device
*
* Return: 0 if all goes good, else appropriate error message.
*/
static int k3_sysctrler_probe(struct udevice *dev)
{
struct k3_sysctrler_privdata *priv;
int ret;
debug("%s(dev=%p)\n", __func__, dev);
priv = dev_get_priv(dev);
ret = k3_of_to_priv(dev, priv);
if (ret) {
dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret);
return ret;
}
priv->desc = (void *)dev_get_driver_data(dev);
priv->seq_nr = 0;
return 0;
}
static int denali_dt_probe(struct udevice *dev)
{
struct denali_nand_info *denali = dev_get_priv(dev);
const struct denali_dt_data *data;
struct clk clk;
struct resource res;
int ret;
data = (void *)dev_get_driver_data(dev);
if (data) {
denali->revision = data->revision;
denali->caps = data->caps;
denali->ecc_caps = data->ecc_caps;
}
denali->dev = dev;
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "nand_data", &res);
if (ret)
return ret;
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_enable(&clk);
if (ret)
return ret;
denali->clk_x_rate = clk_get_rate(&clk);
return denali_init(denali);
}
int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
struct rockchip_saradc_data *data;
data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
pr_err("Dev: %s - can't get address!", dev->name);
return -ENODATA;
}
priv->data = data;
uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
return 0;
}
static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
struct cdns_i2c_platform_data *pdata =
(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
struct clk clk;
int ret;
i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
if (!i2c_bus->regs)
return -ENOMEM;
if (pdata)
i2c_bus->quirks = pdata->quirks;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
i2c_bus->input_freq = clk_get_rate(&clk);
return 0;
}
static int rockchip_i2c_probe(struct udevice *bus)
{
struct rk_i2c *priv = dev_get_priv(bus);
struct rk_i2c_soc_data *soc_data;
struct udevice *pinctrl;
int bus_nr;
int ret;
priv->regs = dev_read_addr_ptr(bus);
soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus);
if (soc_data->controller_type == RK_I2C_LEGACY) {
ret = dev_read_alias_seq(bus, &bus_nr);
if (ret < 0) {
debug("%s: Could not get alias for %s: %d\n",
__func__, bus->name, ret);
return ret;
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
return ret;
}
/* pinctrl will switch I2C to new type */
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
if (ret) {
debug("%s: Failed to switch I2C to new type %s: %d\n",
__func__, bus->name, ret);
return ret;
}
}
return 0;
}
static int uniphier_dwc3_probe(struct udevice *dev)
{
fdt_addr_t base;
void __iomem *regs;
int (*init)(void __iomem *regs);
int ret;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
regs = ioremap(base, SZ_32K);
if (!regs)
return -ENOMEM;
init = (typeof(init))dev_get_driver_data(dev);
ret = init(regs);
if (ret)
dev_err(dev, "failed to init glue layer\n");
iounmap(regs);
return ret;
}
static int altera_tse_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct altera_tse_priv *priv = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev->of_offset;
const char *list, *end;
const fdt32_t *cell;
void *base, *desc_mem = NULL;
unsigned long addr, size;
int parent, addrc, sizec;
int len, idx;
int ret;
priv->dma_type = dev_get_driver_data(dev);
if (priv->dma_type == ALT_SGDMA)
priv->ops = &tse_sgdma_ops;
else
priv->ops = &tse_msgdma_ops;
/*
* decode regs. there are multiple reg tuples, and they need to
* match with reg-names.
*/
parent = fdt_parent_offset(blob, node);
of_bus_default_count_cells(blob, parent, &addrc, &sizec);
list = fdt_getprop(blob, node, "reg-names", &len);
if (!list)
return -ENOENT;
end = list + len;
cell = fdt_getprop(blob, node, "reg", &len);
if (!cell)
return -ENOENT;
idx = 0;
while (list < end) {
addr = fdt_translate_address((void *)blob,
node, cell + idx);
size = fdt_addr_to_cpu(cell[idx + addrc]);
base = map_physmem(addr, size, MAP_NOCACHE);
len = strlen(list);
if (strcmp(list, "control_port") == 0)
priv->mac_dev = base;
else if (strcmp(list, "rx_csr") == 0)
priv->sgdma_rx = base;
else if (strcmp(list, "rx_desc") == 0)
priv->rx_desc = base;
else if (strcmp(list, "rx_resp") == 0)
priv->rx_resp = base;
else if (strcmp(list, "tx_csr") == 0)
priv->sgdma_tx = base;
else if (strcmp(list, "tx_desc") == 0)
priv->tx_desc = base;
else if (strcmp(list, "s1") == 0)
desc_mem = base;
idx += addrc + sizec;
list += (len + 1);
}
/* decode fifo depth */
priv->rx_fifo_depth = fdtdec_get_int(blob, node,
"rx-fifo-depth", 0);
priv->tx_fifo_depth = fdtdec_get_int(blob, node,
"tx-fifo-depth", 0);
/* decode phy */
addr = fdtdec_get_int(blob, node,
"phy-handle", 0);
addr = fdt_node_offset_by_phandle(blob, addr);
priv->phyaddr = fdtdec_get_int(blob, addr,
"reg", 0);
/* init desc */
if (priv->dma_type == ALT_SGDMA) {
len = sizeof(struct alt_sgdma_descriptor) * 4;
if (!desc_mem) {
desc_mem = dma_alloc_coherent(len, &addr);
if (!desc_mem)
return -ENOMEM;
}
memset(desc_mem, 0, len);
priv->tx_desc = desc_mem;
priv->rx_desc = priv->tx_desc +
2 * sizeof(struct alt_sgdma_descriptor);
}
/* allocate recv packet buffer */
priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
if (!priv->rx_buf)
return -ENOMEM;
/* stop controller */
debug("Reset TSE & SGDMAs\n");
altera_tse_stop(dev);
/* start the phy */
priv->interface = pdata->phy_interface;
tse_mdio_init(dev->name, priv);
priv->bus = miiphy_get_dev_by_name(dev->name);
ret = tse_phy_init(priv, dev);
return ret;
}
static int omap_hsmmc_set_ios(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
#else
static int omap_hsmmc_set_ios(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
#endif
struct hsmmc *mmc_base;
unsigned int dsor = 0;
ulong start;
mmc_base = priv->base_addr;
/* configue bus width */
switch (mmc->bus_width) {
case 8:
writel(readl(&mmc_base->con) | DTW_8_BITMODE,
&mmc_base->con);
break;
case 4:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
&mmc_base->hctl);
break;
case 1:
default:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
&mmc_base->hctl);
break;
}
/* configure clock with 96Mhz system clock.
*/
if (mmc->clock != 0) {
dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
dsor++;
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for ics!\n", __func__);
return -ETIMEDOUT;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
return 0;
}
#ifdef OMAP_HSMMC_USE_GPIO
#if CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_getcd(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value;
value = dm_gpio_get_value(&priv->cd_gpio);
/* if no CD return as 1 */
if (value < 0)
return 1;
if (priv->cd_inverted)
return !value;
return value;
}
static int omap_hsmmc_getwp(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value;
value = dm_gpio_get_value(&priv->wp_gpio);
/* if no WP return as 0 */
if (value < 0)
return 0;
return value;
}
#else
static int omap_hsmmc_getcd(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
int cd_gpio;
/* if no CD return as 1 */
cd_gpio = priv->cd_gpio;
if (cd_gpio < 0)
return 1;
/* NOTE: assumes card detect signal is active-low */
return !gpio_get_value(cd_gpio);
}
static int omap_hsmmc_getwp(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
int wp_gpio;
/* if no WP return as 0 */
wp_gpio = priv->wp_gpio;
if (wp_gpio < 0)
return 0;
/* NOTE: assumes write protect signal is active-high */
return gpio_get_value(wp_gpio);
}
#endif
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
static const struct dm_mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
#ifdef OMAP_HSMMC_USE_GPIO
.get_cd = omap_hsmmc_getcd,
.get_wp = omap_hsmmc_getwp,
#endif
};
#else
static const struct mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
.init = omap_hsmmc_init_setup,
#ifdef OMAP_HSMMC_USE_GPIO
.getcd = omap_hsmmc_getcd,
.getwp = omap_hsmmc_getwp,
#endif
};
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc;
struct omap_hsmmc_data *priv;
struct mmc_config *cfg;
uint host_caps_val;
priv = malloc(sizeof(*priv));
if (priv == NULL)
return -1;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_index) {
case 0:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
default:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
#ifdef OMAP_HSMMC_USE_GPIO
/* on error gpio values are set to -1, which is what we want */
priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
#endif
cfg = &priv->cfg;
cfg->name = "OMAP SD/MMC";
cfg->ops = &omap_hsmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = host_caps_val & ~host_caps_mask;
cfg->f_min = 400000;
if (f_max != 0)
cfg->f_max = f_max;
else {
if (cfg->host_caps & MMC_MODE_HS) {
if (cfg->host_caps & MMC_MODE_HS_52MHz)
cfg->f_max = 52000000;
else
cfg->f_max = 26000000;
} else
cfg->f_max = 20000000;
}
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
cfg->b_max = 1;
#endif
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
return 0;
}
#else
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
struct omap2_mmc_platform_config *data =
(struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
plat->base_addr = map_physmem(devfdt_get_addr(dev),
sizeof(struct hsmmc *),
MAP_NOCACHE) + data->reg_offset;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
if (val < 0) {
printf("error: bus-width property missing\n");
return -ENOENT;
}
switch (val) {
case 0x8:
cfg->host_caps |= MMC_MODE_8BIT;
case 0x4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
default:
printf("error: invalid bus-width property\n");
return -ENOENT;
}
cfg->f_min = 400000;
cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#ifdef OMAP_HSMMC_USE_GPIO
plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
#endif
return 0;
}
#endif
#ifdef CONFIG_BLK
static int omap_hsmmc_bind(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#endif
static int omap_hsmmc_probe(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
struct mmc *mmc;
cfg->name = "OMAP SD/MMC";
priv->base_addr = plat->base_addr;
#ifdef OMAP_HSMMC_USE_GPIO
priv->cd_inverted = plat->cd_inverted;
#endif
#ifdef CONFIG_BLK
mmc = &plat->mmc;
#else
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
#endif
#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
mmc->dev = dev;
upriv->mmc = mmc;
return omap_hsmmc_init_setup(mmc);
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
.reg_offset = 0,
};
static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
.reg_offset = 0x100,
};
static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
.reg_offset = 0x100,
};
static const struct udevice_id omap_hsmmc_ids[] = {
{
.compatible = "ti,omap3-hsmmc",
.data = (ulong)&omap3_mmc_pdata
},
{
.compatible = "ti,omap4-hsmmc",
.data = (ulong)&omap4_mmc_pdata
},
{
.compatible = "ti,am33xx-hsmmc",
.data = (ulong)&am33xx_mmc_pdata
},
{ }
};
static int palmas_smps_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
struct udevice *parent;
int idx;
uc_pdata = dev_get_uclass_platdata(dev);
parent = dev_get_parent(dev);
int type = dev_get_driver_data(parent);
uc_pdata->type = REGULATOR_TYPE_BUCK;
switch (type) {
case PALMAS:
case TPS659038:
switch (dev->driver_data) {
case 123:
case 12:
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][0];
uc_pdata->volt_reg = palmas_smps_volt[type][0];
break;
case 3:
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][1];
uc_pdata->volt_reg = palmas_smps_volt[type][1];
break;
case 45:
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][2];
uc_pdata->volt_reg = palmas_smps_volt[type][2];
break;
case 6:
case 7:
case 8:
case 9:
case 10:
idx = dev->driver_data - 3;
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
uc_pdata->volt_reg = palmas_smps_volt[type][idx];
break;
default:
printf("Wrong ID for regulator\n");
}
break;
case TPS65917:
switch (dev->driver_data) {
case 1:
case 2:
case 3:
case 4:
case 5:
idx = dev->driver_data - 1;
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
uc_pdata->volt_reg = palmas_smps_volt[type][idx];
break;
case 12:
idx = 0;
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
uc_pdata->volt_reg = palmas_smps_volt[type][idx];
break;
default:
printf("Wrong ID for regulator\n");
}
break;
default:
printf("Invalid PMIC ID\n");
}
return 0;
}
static int denali_dt_probe(struct udevice *dev)
{
struct denali_nand_info *denali = dev_get_priv(dev);
const struct denali_dt_data *data;
struct clk clk, clk_x, clk_ecc;
struct resource res;
int ret;
data = (void *)dev_get_driver_data(dev);
if (data) {
denali->revision = data->revision;
denali->caps = data->caps;
denali->ecc_caps = data->ecc_caps;
}
denali->dev = dev;
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "nand_data", &res);
if (ret)
return ret;
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
ret = clk_get_by_name(dev, "nand", &clk);
if (ret)
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_get_by_name(dev, "nand_x", &clk_x);
if (ret)
clk_x.dev = NULL;
ret = clk_get_by_name(dev, "ecc", &clk_ecc);
if (ret)
clk_ecc.dev = NULL;
ret = clk_enable(&clk);
if (ret)
return ret;
if (clk_x.dev) {
ret = clk_enable(&clk_x);
if (ret)
return ret;
}
if (clk_ecc.dev) {
ret = clk_enable(&clk_ecc);
if (ret)
return ret;
}
if (clk_x.dev) {
denali->clk_rate = clk_get_rate(&clk);
denali->clk_x_rate = clk_get_rate(&clk_x);
} else {
/*
* Hardcode the clock rates for the backward compatibility.
* This works for both SOCFPGA and UniPhier.
*/
dev_notice(dev,
"necessary clock is missing. default clock rates are used.\n");
denali->clk_rate = 50000000;
denali->clk_x_rate = 200000000;
}
ret = reset_get_bulk(dev, &denali->resets);
if (ret)
dev_warn(dev, "Can't get reset: %d\n", ret);
else
reset_deassert_bulk(&denali->resets);
return denali_init(denali);
}
static int pca953x_probe(struct udevice *dev)
{
struct pca953x_info *info = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
char name[32], *str;
int addr;
ulong driver_data;
int ret;
if (!info) {
dev_err(dev, "platdata not ready\n");
return -ENOMEM;
}
if (!chip) {
dev_err(dev, "i2c not ready\n");
return -ENODEV;
}
addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
if (addr == 0)
return -ENODEV;
info->addr = addr;
driver_data = dev_get_driver_data(dev);
info->gpio_count = driver_data & PCA_GPIO_MASK;
if (info->gpio_count > MAX_BANK * BANK_SZ) {
dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
return -EINVAL;
}
info->chip_type = PCA_CHIP_TYPE(driver_data);
if (info->chip_type != PCA953X_TYPE) {
dev_err(dev, "Only support PCA953X chip type now.\n");
return -EINVAL;
}
info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
if (ret) {
dev_err(dev, "Error reading output register\n");
return ret;
}
ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
if (ret) {
dev_err(dev, "Error reading direction register\n");
return ret;
}
snprintf(name, sizeof(name), "gpio@%x_", info->addr);
str = strdup(name);
if (!str)
return -ENOMEM;
uc_priv->bank_name = str;
uc_priv->gpio_count = info->gpio_count;
dev_dbg(dev, "%s is ready\n", str);
return 0;
}
static int sh_pfc_pinctrl_probe(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
enum sh_pfc_model model = dev_get_driver_data(dev);
fdt_addr_t base;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
if (!priv->pfc.regs)
return -ENOMEM;
#ifdef CONFIG_PINCTRL_PFC_R8A7790
if (model == SH_PFC_R8A7790)
priv->pfc.info = &r8a7790_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7791
if (model == SH_PFC_R8A7791)
priv->pfc.info = &r8a7791_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7792
if (model == SH_PFC_R8A7792)
priv->pfc.info = &r8a7792_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7793
if (model == SH_PFC_R8A7793)
priv->pfc.info = &r8a7793_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7794
if (model == SH_PFC_R8A7794)
priv->pfc.info = &r8a7794_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7795
if (model == SH_PFC_R8A7795)
priv->pfc.info = &r8a7795_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7796
if (model == SH_PFC_R8A7796)
priv->pfc.info = &r8a7796_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
if (model == SH_PFC_R8A77970)
priv->pfc.info = &r8a77970_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77990
if (model == SH_PFC_R8A77990)
priv->pfc.info = &r8a77990_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77995
if (model == SH_PFC_R8A77995)
priv->pfc.info = &r8a77995_pinmux_info;
#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
sh_pfc_map_pins(&priv->pfc, &priv->pmx);
return 0;
}
