static int stm32_reset_probe(struct udevice *dev)
{
struct stm32_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE) {
/* for MFD, get address of parent */
priv->base = dev_read_addr(dev->parent);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
}
return 0;
}
static int sunxi_sata_probe(struct udevice *dev)
{
ulong base;
u8 *reg;
int ret;
base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE) {
debug("%s: Failed to find address (err=%d\n)", __func__, ret);
return -EINVAL;
}
reg = (u8 *)base;
ret = sunxi_ahci_phy_init(reg);
if (ret) {
debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
return ret;
}
ret = ahci_probe_scsi(dev, base);
if (ret) {
debug("%s: Failed to probe (err=%d\n)", __func__, ret);
return ret;
}
return 0;
}
static int sb_eth_raw_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
const char *ifname;
u32 local;
int ret;
pdata->iobase = dev_read_addr(dev);
ifname = dev_read_string(dev, "host-raw-interface");
if (ifname) {
strncpy(priv->host_ifname, ifname, IFNAMSIZ);
printf(": Using %s from DT\n", priv->host_ifname);
}
if (dev_read_u32(dev, "host-raw-interface-idx",
&priv->host_ifindex) < 0) {
priv->host_ifindex = 0;
} else {
ret = sandbox_eth_raw_os_idx_to_name(priv);
if (ret < 0)
return ret;
printf(": Using interface index %d from DT (%s)\n",
priv->host_ifindex, priv->host_ifname);
}
local = sandbox_eth_raw_os_is_local(priv->host_ifname);
if (local < 0)
return local;
priv->local = local;
return 0;
}
int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE];
struct dc_ctlr *disp_ctrl;
unsigned long dc_int_mask;
int ret;
debug("%s\n", __func__);
/* Use the first display controller */
disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
/* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
SUPER_STATE1_ASY_ORMODE_SAFE |
SUPER_STATE1_ATTACHED_YES);
tegra_dc_sor_super_update(sor);
tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);
if (tegra_dc_sor_poll_register(sor, TEST,
TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
TEST_ACT_HEAD_OPMODE_SLEEP, 100,
TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
debug("dc timeout waiting for OPMOD = SLEEP\n");
ret = -ETIMEDOUT;
goto err;
}
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
SUPER_STATE1_ASY_ORMODE_SAFE |
SUPER_STATE1_ATTACHED_NO);
/* Mask DC interrupts during the 2 dummy frames required for detach */
dc_int_mask = readl(&disp_ctrl->cmd.int_mask);
writel(0, &disp_ctrl->cmd.int_mask);
/* Stop DC->SOR path */
tegra_dc_sor_enable_sor(disp_ctrl, false);
ret = tegra_dc_sor_general_act(disp_ctrl);
if (ret)
goto err;
/* Stop DC */
writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);
ret = tegra_dc_sor_general_act(disp_ctrl);
if (ret)
goto err;
tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);
writel(dc_int_mask, &disp_ctrl->cmd.int_mask);
return 0;
err:
debug("%s: ret=%d\n", __func__, ret);
return ret;
}
static int pl031_ofdata_to_platdata(struct udevice *dev)
{
struct pl031_platdata *pdata = dev_get_platdata(dev);
pdata->base = dev_read_addr(dev);
return 0;
}
static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
return 0;
}
static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
{
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
platdata->regs = (struct uart_sifive *)dev_read_addr(dev);
if (IS_ERR(platdata->regs))
return PTR_ERR(platdata->regs);
return 0;
}
static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
priv->regs = (struct uart_zynq *)dev_read_addr(dev);
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
return 0;
}
static int stm32_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_timer_priv *priv = dev_get_priv(dev);
struct stm32_timer_regs *regs;
struct clk clk;
fdt_addr_t addr;
int ret;
u32 rate, psc;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = (struct stm32_timer_regs *)addr;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
regs = priv->base;
/* Stop the timer */
clrbits_le32(®s->cr1, CR1_CEN);
/* get timer clock */
rate = clk_get_rate(&clk);
/* we set timer prescaler to obtain a 1MHz timer counter frequency */
psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
writel(psc, ®s->psc);
/* Set timer frequency to 1MHz */
uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
/* Configure timer for auto-reload */
setbits_le32(®s->cr1, CR1_ARPE);
/* load value for auto reload */
writel(GPT_FREE_RUNNING, ®s->arr);
/* start timer */
setbits_le32(®s->cr1, CR1_CEN);
/* Update generation */
setbits_le32(®s->egr, EGR_UG);
return 0;
}
static int pm8916_probe(struct udevice *dev)
{
struct pm8916_priv *priv = dev_get_priv(dev);
priv->usid = dev_read_addr(dev);
if (priv->usid == FDT_ADDR_T_NONE)
return -EINVAL;
return 0;
}
static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name;
host->ioaddr = (void *)dev_read_addr(dev);
host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
plat->f_max = dev_read_u32_default(dev, "max-frequency", 0);
return 0;
}
static int gpio_dwapb_bind(struct udevice *dev)
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
struct udevice *subdev;
fdt_addr_t base;
int ret, bank = 0;
ofnode node;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
}
for (node = dev_read_first_subnode(dev); ofnode_valid(node);
node = dev_read_next_subnode(node)) {
if (!ofnode_read_bool(node, "gpio-controller"))
continue;
plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
plat->base = base;
plat->bank = bank;
plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
if (ofnode_read_string_index(node, "bank-name", 0,
&plat->name)) {
/*
* Fall back to node name. This means accessing pins
* via bank name won't work.
*/
plat->name = ofnode_get_name(node);
}
ret = device_bind(dev, dev->driver, plat->name,
plat, -1, &subdev);
if (ret)
return ret;
dev->node = node;
bank++;
}
return 0;
}
static int samsung_i2s_ofdata_to_platdata(struct udevice *dev)
{
struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
ulong base;
/*
* Get the pre-defined sound specific values from FDT.
* All of these are expected to be correct otherwise
* wrong register values in i2s setup parameters
* may result in no sound play.
*/
base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE) {
debug("%s: Missing i2s base\n", __func__);
return -EINVAL;
}
priv->base_address = base;
if (dev_read_u32u(dev, "samsung,i2s-epll-clock-frequency",
&priv->audio_pll_clk))
goto err;
debug("audio_pll_clk = %d\n", priv->audio_pll_clk);
if (dev_read_u32u(dev, "samsung,i2s-sampling-rate",
&priv->samplingrate))
goto err;
debug("samplingrate = %d\n", priv->samplingrate);
if (dev_read_u32u(dev, "samsung,i2s-bits-per-sample",
&priv->bitspersample))
goto err;
debug("bitspersample = %d\n", priv->bitspersample);
if (dev_read_u32u(dev, "samsung,i2s-channels", &priv->channels))
goto err;
debug("channels = %d\n", priv->channels);
if (dev_read_u32u(dev, "samsung,i2s-lr-clk-framesize", &priv->rfs))
goto err;
debug("rfs = %d\n", priv->rfs);
if (dev_read_u32u(dev, "samsung,i2s-bit-clk-framesize", &priv->bfs))
goto err;
debug("bfs = %d\n", priv->bfs);
if (dev_read_u32u(dev, "samsung,i2s-id", &priv->id))
goto err;
debug("id = %d\n", priv->id);
return 0;
err:
debug("fail to get sound i2s node properties\n");
return -EINVAL;
}
DEBUG_UART_FUNCS
#endif
#if CONFIG_IS_ENABLED(DM_SERIAL)
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
struct clk clk;
int err;
/* try Processor Local Bus device first */
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
plat->reg_shift = 2;
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
if (!IS_ERR_VALUE(err))
plat->clock = err;
} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("omap serial failed to get clock\n");
return err;
}
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("omap serial clock not defined\n");
return -EINVAL;
}
plat->fcr = UART_FCR_DEFVAL;
return 0;
}
static int pm8916_gpio_probe(struct udevice *dev)
{
struct pm8916_gpio_bank *priv = dev_get_priv(dev);
int reg;
priv->pid = dev_read_addr(dev);
if (priv->pid == FDT_ADDR_T_NONE)
return -EINVAL;
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != 0x10)
return -ENODEV;
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
if (reg != 0x5 && reg != 0x1)
return -ENODEV;
return 0;
}
int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
struct rockchip_saradc_data *data;
data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
pr_err("Dev: %s - can't get address!", dev->name);
return -ENODATA;
}
priv->data = data;
uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
return 0;
}
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
int ret;
priv->base = (void *)dev_read_addr(dev);
priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
if (IS_ERR(priv->pmc_base))
return PTR_ERR(priv->pmc_base);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);
if (ret) {
debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
dev->name, ret);
return ret;
}
return 0;
}
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("phy-handle does exist %s\n", dev->name);
priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
priv->phy_of_node = phandle_args.node;
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
"max-speed",
SPEED_1000);
}
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
struct cdns_i2c_platform_data *pdata =
(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
struct clk clk;
int ret;
i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
if (!i2c_bus->regs)
return -ENOMEM;
if (pdata)
i2c_bus->quirks = pdata->quirks;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
i2c_bus->input_freq = clk_get_rate(&clk);
return 0;
}
static int stm32_sdmmc2_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
int ret;
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
if (dev_read_bool(dev, "st,negedge"))
priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
if (dev_read_bool(dev, "st,dirpol"))
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
goto clk_free;
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
if (ret)
goto clk_disable;
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
GPIOD_IS_IN);
cfg->f_min = 400000;
cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->name = "STM32 SDMMC2";
cfg->host_caps = 0;
if (cfg->f_max > 25000000)
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_read_u32_default(dev, "bus-width", 1)) {
case 8:
cfg->host_caps |= MMC_MODE_8BIT;
case 4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
default:
pr_err("invalid \"bus-width\" property, force to 1\n");
}
upriv->mmc = &plat->mmc;
return 0;
clk_disable:
clk_disable(&priv->clk);
clk_free:
clk_free(&priv->clk);
return ret;
}
static int gpio_stm32_probe(struct udevice *dev)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct clk clk;
fdt_addr_t addr;
int ret;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (struct stm32_gpio_regs *)addr;
#ifndef CONFIG_SPL_BUILD
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ofnode_phandle_args args;
const char *name;
int i;
name = dev_read_string(dev, "st,bank-name");
if (!name)
return -EINVAL;
uc_priv->bank_name = name;
i = 0;
ret = dev_read_phandle_with_args(dev, "gpio-ranges",
NULL, 3, i, &args);
if (ret == -ENOENT) {
uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
}
while (ret != -ENOENT) {
priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
args.args[0]);
uc_priv->gpio_count += args.args[2];
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
++i, &args);
}
dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
priv->gpio_range);
#endif
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
debug("clock enabled for device %s\n", dev->name);
return 0;
}
static int pca953x_probe(struct udevice *dev)
{
struct pca953x_info *info = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[32], label[8], *str;
int addr;
ulong driver_data;
int ret;
int size;
const u8 *tmp;
addr = dev_read_addr(dev);
if (addr == 0)
return -ENODEV;
info->addr = addr;
driver_data = dev_get_driver_data(dev);
info->gpio_count = driver_data & PCA_GPIO_MASK;
if (info->gpio_count > MAX_BANK * BANK_SZ) {
dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
return -EINVAL;
}
info->chip_type = PCA_CHIP_TYPE(driver_data);
if (info->chip_type != PCA953X_TYPE) {
dev_err(dev, "Only support PCA953X chip type now.\n");
return -EINVAL;
}
info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
if (ret) {
dev_err(dev, "Error reading output register\n");
return ret;
}
ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
if (ret) {
dev_err(dev, "Error reading direction register\n");
return ret;
}
tmp = dev_read_prop(dev, "label", &size);
if (tmp) {
memcpy(label, tmp, sizeof(label) - 1);
label[sizeof(label) - 1] = '\0';
snprintf(name, sizeof(name), "%s@%x_", label, info->addr);
} else {
snprintf(name, sizeof(name), "gpio@%x_", info->addr);
}
str = strdup(name);
if (!str)
return -ENOMEM;
uc_priv->bank_name = str;
uc_priv->gpio_count = info->gpio_count;
dev_dbg(dev, "%s is ready\n", str);
return 0;
}
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
int err;
/* try Processor Local Bus device first */
addr = dev_read_addr(dev);
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
/* we prefer to use a memory-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
dev_of_offset(dev),
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
return ret;
}
ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
addr = bar;
}
#endif
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
plat->base = addr;
#else
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
#endif
plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
if (!IS_ERR_VALUE(err))
plat->clock = err;
} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("ns16550 failed to get clock\n");
return err;
}
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
}
plat->fcr = UART_FCR_DEFVAL;
if (port_type == PORT_JZ4780)
plat->fcr |= UART_FCR_UME;
return 0;
}
void *dev_read_addr_ptr(struct udevice *dev)
{
fdt_addr_t addr = dev_read_addr(dev);
return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0);
}
static int ehci_usb_probe(struct udevice *dev)
{
struct generic_ehci *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int i, err, ret, clock_nb, reset_nb;
err = 0;
priv->clock_count = 0;
clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
"#clock-cells");
if (clock_nb > 0) {
priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
GFP_KERNEL);
if (!priv->clocks)
return -ENOMEM;
for (i = 0; i < clock_nb; i++) {
err = clk_get_by_index(dev, i, &priv->clocks[i]);
if (err < 0)
break;
err = clk_enable(&priv->clocks[i]);
if (err) {
pr_err("failed to enable clock %d\n", i);
clk_free(&priv->clocks[i]);
goto clk_err;
}
priv->clock_count++;
}
} else {
if (clock_nb != -ENOENT) {
pr_err("failed to get clock phandle(%d)\n", clock_nb);
return clock_nb;
}
}
priv->reset_count = 0;
reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
"#reset-cells");
if (reset_nb > 0) {
priv->resets = devm_kcalloc(dev, reset_nb,
sizeof(struct reset_ctl),
GFP_KERNEL);
if (!priv->resets)
return -ENOMEM;
for (i = 0; i < reset_nb; i++) {
err = reset_get_by_index(dev, i, &priv->resets[i]);
if (err < 0)
break;
if (reset_deassert(&priv->resets[i])) {
pr_err("failed to deassert reset %d\n", i);
reset_free(&priv->resets[i]);
goto reset_err;
}
priv->reset_count++;
}
} else {
if (reset_nb != -ENOENT) {
pr_err("failed to get reset phandle(%d)\n", reset_nb);
goto clk_err;
}
}
err = generic_phy_get_by_index(dev, 0, &priv->phy);
if (err) {
if (err != -ENOENT) {
pr_err("failed to get usb phy\n");
goto reset_err;
}
} else {
err = generic_phy_init(&priv->phy);
if (err) {
pr_err("failed to init usb phy\n");
goto reset_err;
}
}
hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
err = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
if (err)
goto phy_err;
return 0;
phy_err:
if (generic_phy_valid(&priv->phy)) {
ret = generic_phy_exit(&priv->phy);
if (ret)
pr_err("failed to release phy\n");
}
reset_err:
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
pr_err("failed to assert all resets\n");
clk_err:
ret = clk_release_all(priv->clocks, priv->clock_count);
if (ret)
pr_err("failed to disable all clocks\n");
return err;
}
static int display_init(struct udevice *dev, void *lcdbase,
int fb_bits_per_pixel, struct display_timing *timing)
{
struct display_plat *disp_uc_plat;
struct dc_ctlr *dc_ctlr;
struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */
u32 plld_rate;
int ret;
/*
* Before we probe the display device (eDP), tell it that this device
* is the source of the display data.
*/
ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
if (ret) {
debug("%s: device '%s' display not found (ret=%d)\n", __func__,
dev->name, ret);
return ret;
}
disp_uc_plat = dev_get_uclass_platdata(dp_dev);
debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
disp_uc_plat);
disp_uc_plat->src_dev = dev;
ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
if (ret) {
debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
return ret;
}
dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
if (ret) {
debug("%s: Failed to decode EDID, using defaults\n", __func__);
dump_config(panel_bpp, timing);
}
/*
* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
* update_display_mode() for detail.
*/
plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
if (plld_rate == 0) {
printf("dc: clock init failed\n");
return -EIO;
} else if (plld_rate != timing->pixelclock.typ * 2) {
debug("dc: plld rounded to %u\n", plld_rate);
timing->pixelclock.typ = plld_rate / 2;
}
/* Init dc */
ret = tegra_dc_init(dc_ctlr);
if (ret) {
debug("dc: init failed\n");
return ret;
}
/* Configure dc mode */
ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
if (ret) {
debug("dc: failed to configure display mode\n");
return ret;
}
/* Enable dp */
ret = display_enable(dp_dev, panel_bpp, timing);
if (ret) {
debug("dc: failed to enable display: ret=%d\n", ret);
return ret;
}
ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
if (ret) {
debug("dc: failed to update window\n");
return ret;
}
debug("%s: ready\n", __func__);
return 0;
}
static int tegra_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct tegra_mmc_plat *plat = dev_get_platdata(dev);
struct tegra_mmc_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
int bus_width, ret;
cfg->name = dev->name;
bus_width = dev_read_u32_default(dev, "bus-width", 1);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = 0;
if (bus_width == 8)
cfg->host_caps |= MMC_MODE_8BIT;
if (bus_width >= 4)
cfg->host_caps |= MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* min freq is for card identification, and is the highest
* low-speed SDIO card frequency (actually 400KHz)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
*/
cfg->f_min = 375000;
cfg->f_max = 48000000;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
priv->reg = (void *)dev_read_addr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {
debug("reset_get_by_name() failed: %d\n", ret);
return ret;
}
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret) {
debug("clk_get_by_index() failed: %d\n", ret);
return ret;
}
ret = reset_assert(&priv->reset_ctl);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
ret = clk_set_rate(&priv->clk, 20000000);
if (IS_ERR_VALUE(ret))
return ret;
ret = reset_deassert(&priv->reset_ctl);
if (ret)
return ret;
/* These GPIOs are optional */
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
GPIOD_IS_OUT);
if (dm_gpio_is_valid(&priv->pwr_gpio))
dm_gpio_set_value(&priv->pwr_gpio, 1);
upriv->mmc = &plat->mmc;
return tegra_mmc_init(dev);
}
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
const struct tegra_dp_link_config *link_cfg,
const struct display_timing *timing)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
struct dc_ctlr *disp_ctrl;
u32 reg_val;
/* Use the first display controller */
debug("%s\n", __func__);
disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
writel(0x9f, &disp_ctrl->cmd.state_ctrl);
writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
&disp_ctrl->cmd.disp_pow_ctrl);
reg_val = tegra_sor_readl(sor, TEST);
if (reg_val & TEST_ATTACHED_TRUE)
return -EEXIST;
tegra_sor_writel(sor, SUPER_STATE1,
SUPER_STATE1_ATTACHED_NO);
/*
* Enable display2sor clock at least 2 cycles before DC start,
* to clear sor internal valid signal.
*/
writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
writel(0, &disp_ctrl->disp.disp_win_opt);
writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
/* Attach head */
tegra_dc_sor_update(sor);
tegra_sor_writel(sor, SUPER_STATE1,
SUPER_STATE1_ATTACHED_YES);
tegra_sor_writel(sor, SUPER_STATE1,
SUPER_STATE1_ATTACHED_YES |
SUPER_STATE1_ASY_HEAD_OP_AWAKE |
SUPER_STATE1_ASY_ORMODE_NORMAL);
tegra_dc_sor_super_update(sor);
/* Enable dc */
reg_val = readl(&disp_ctrl->cmd.state_access);
writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
&disp_ctrl->cmd.disp_cmd);
writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
writel(reg_val, &disp_ctrl->cmd.state_access);
if (tegra_dc_sor_poll_register(sor, TEST,
TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
TEST_ACT_HEAD_OPMODE_AWAKE,
100,
TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
printf("dc timeout waiting for OPMOD = AWAKE\n");
return -ETIMEDOUT;
} else {
debug("%s: sor is attached\n", __func__);
}
#if DEBUG_SOR
dump_sor_reg(sor);
#endif
debug("%s: ret=%d\n", __func__, 0);
return 0;
}
