int adc_qmsi_init(struct device *dev)
{
qm_adc_config_t cfg;
struct adc_info *info = dev->driver_data;
dev->driver_api = &api_funcs;
/* Enable the ADC and set the clock divisor */
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_ADC |
CLK_PERIPH_ADC_REGISTER);
/* ADC clock divider*/
clk_adc_set_div(CONFIG_ADC_QMSI_CLOCK_RATIO);
/* Set up config */
/* Clock cycles between the start of each sample */
cfg.window = CONFIG_ADC_QMSI_SERIAL_DELAY;
cfg.resolution = CONFIG_ADC_QMSI_SAMPLE_WIDTH;
qm_adc_set_config(QM_ADC_0, &cfg);
device_sync_call_init(&info->sync);
nano_sem_init(&info->sem);
nano_sem_give(&info->sem);
info->state = ADC_STATE_IDLE;
adc_config_irq();
return 0;
}
int spi_dw_init(struct device *dev)
{
struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
_clock_config(dev);
_clock_on(dev);
#ifndef CONFIG_SOC_QUARK_SE_SS
if (read_ssi_comp_version(info->regs) != DW_SSI_COMP_VERSION) {
_clock_off(dev);
return DEV_NOT_CONFIG;
}
#endif
dev->driver_api = &dw_spi_api;
info->config_func();
device_sync_call_init(&spi->sync);
_spi_config_cs(dev);
/* Masking interrupt and making sure controller is disabled */
write_imr(DW_SPI_IMR_MASK, info->regs);
clear_bit_ssienr(info->regs);
DBG("Designware SPI driver initialized on device: %p\n", dev);
return DEV_OK;
}
int i2c_qse_ss_initialize(struct device *dev)
{
struct i2c_qse_ss_rom_config * const rom = dev->config->config_info;
struct i2c_qse_ss_dev_config * const dw = dev->driver_data;
dev->driver_api = &ss_funcs;
if (rom->config_func) {
rom->config_func(dev);
}
/* Enable clock for controller so we can talk to it */
_i2c_qse_ss_reg_write_or(dev, REG_CON, IC_CON_CLK_ENA);
device_sync_call_init(&dw->sync);
if (i2c_qse_ss_runtime_configure(dev, dw->app_config.raw) != DEV_OK) {
DBG("I2C_SS: Cannot set default configuration 0x%x\n",
dw->app_config.raw);
return DEV_NOT_CONFIG;
}
dw->state = I2C_QSE_SS_STATE_READY;
return DEV_OK;
}
static int spi_qmsi_init(struct device *dev)
{
struct spi_qmsi_config *spi_config = dev->config->config_info;
struct spi_qmsi_runtime *context = dev->driver_data;
dev->driver_api = &spi_qmsi_api;
switch (spi_config->spi) {
case QM_SPI_MST_0:
IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_0_IRQ,
CONFIG_SPI_QMSI_PORT_0_PRI, qm_spi_master_0_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(CONFIG_SPI_QMSI_PORT_0_IRQ);
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
QM_SCSS_INT->int_spi_mst_0_mask &= ~BIT(0);
break;
case QM_SPI_MST_1:
IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_1_IRQ,
CONFIG_SPI_QMSI_PORT_1_PRI, qm_spi_master_1_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(CONFIG_SPI_QMSI_PORT_1_IRQ);
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
QM_SCSS_INT->int_spi_mst_1_mask &= ~BIT(0);
break;
default:
return DEV_FAIL;
}
context->gpio_cs = gpio_cs_init(spi_config);
device_sync_call_init(&context->sync);
return DEV_OK;
}
int i2c_dw_initialize(struct device *port)
{
struct i2c_dw_rom_config const * const rom = port->config->config_info;
struct i2c_dw_dev_config * const dev = port->driver_data;
volatile struct i2c_dw_registers *regs;
if (!i2c_dw_pci_setup(port)) {
port->driver_api = NULL;
return -EPERM;
}
device_sync_call_init(&dev->sync);
regs = (struct i2c_dw_registers *) rom->base_address;
/* verify that we have a valid DesignWare register first */
if (regs->ic_comp_type != I2C_DW_MAGIC_KEY) {
port->driver_api = NULL;
DBG("I2C: DesignWare magic key not found, check base address.");
DBG(" Stopping initialization\n");
return -EPERM;
}
/*
* grab the default value on initialization. This should be set to the
* IC_MAX_SPEED_MODE in the hardware. If it does support high speed we
* can move provide support for it
*/
if (regs->ic_con.bits.speed == I2C_DW_SPEED_HIGH) {
DBG("I2C: high speed supported\n");
dev->support_hs_mode = true;
} else {
DBG("I2C: high speed NOT supported\n");
dev->support_hs_mode = false;
}
rom->config_func(port);
if (i2c_dw_runtime_configure(port, dev->app_config.raw) != 0) {
DBG("I2C: Cannot set default configuration 0x%x\n",
dev->app_config.raw);
return -EPERM;
}
dev->state = I2C_DW_STATE_READY;
return 0;
}
int spi_k64_init(struct device *dev)
{
struct spi_k64_config *info = dev->config->config_info;
struct spi_k64_data *data = dev->driver_data;
uint32_t mcr;
dev->driver_api = &k64_spi_api;
/* Enable module clocking */
sys_set_bit(info->clk_gate_reg, info->clk_gate_bit);
/*
* Ensure module operation is stopped and enabled before writing anything
* more to the registers.
* (Clear MCR[MDIS] and set MCR[HALT].)
*/
DBG("halt\n");
mcr = SPI_K64_MCR_HALT;
sys_write32(mcr, (info->regs + SPI_K64_REG_MCR));
while (sys_read32(info->regs + SPI_K64_REG_SR) & SPI_K64_SR_TXRXS) {
DBG("SPI Controller dev %p is running. Waiting for Halt.\n", dev);
}
/* Clear Tx and Rx FIFOs */
mcr |= (SPI_K64_MCR_CLR_RXF | SPI_K64_MCR_CLR_TXF);
DBG("fifo clr\n");
sys_write32(mcr, (info->regs + SPI_K64_REG_MCR));
/* Set master mode */
mcr = SPI_K64_MCR_MSTR | SPI_K64_MCR_HALT;
DBG("master mode\n");
sys_write32(mcr, (info->regs + SPI_K64_REG_MCR));
/* Disable SPI module interrupt generation */
DBG("irq disable\n");
sys_write32(0, (info->regs + SPI_K64_REG_RSER));
/* Clear status */
DBG("status clr\n");
sys_write32((SPI_K64_SR_RFDF | SPI_K64_SR_RFOF | SPI_K64_SR_TFUF |
SPI_K64_SR_EOQF | SPI_K64_SR_TCF),
(info->regs + SPI_K64_REG_SR));
/* Set up the synchronous call mechanism */
device_sync_call_init(&data->sync_info);
/* Configure and enable SPI module IRQs */
info->config_func();
irq_enable(info->irq);
/*
* Enable Rx overflow interrupt generation.
* Note that Tx underflow is only generated when in slave mode.
*/
DBG("rxfifo overflow enable\n");
sys_write32(SPI_K64_RSER_RFOF_RE, (info->regs + SPI_K64_REG_RSER));
DBG("K64 SPI Driver initialized on device: %p\n", dev);
/* operation remains disabled (MCR[HALT] = 1)*/
return DEV_OK;
}
