void start_settings(void)
{
// Init MMU
CP15_Mmu(FALSE); // Disable MMU
// Privileged permissions User permissions AP
// Read-only Read-only 0
CP15_SysProt(FALSE);
CP15_RomProt(TRUE);
CP15_InitMmuTtb(TtSB,TtTB); // Build L1 and L2 Translation tables
CP15_SetTtb(L1Table); // Set base address of the L1 Translation table
CP15_SetDomain( (DomainManager << 2*1) | (DomainClient << 0)); // Set domains
CP15_Mmu(TRUE); // Enable MMU
CP15_Cache(TRUE); // Enable ICache,DCache
/* Disable interrupts in ARM core */
disable_irq_fiq();
InitializeInterruptSystem();
// Enable IRQ interrupts in the ARM core
enable_irq_fiq();
initCallBackElement();//инит callBackElement
initTimers();//инит таймеров
initTimers_WL();//TIMERS INIT РЛ
WideLogActual = &(pActualCMD[DQUADRO]);//командный массив расшир логики(вторая половина)
ResetSystemMenu();//сбросить сист меню
timing = 0;
}//start_settings(void)
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
void c_entry(void)
{
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Setup miscellaneous board functions */
ea3250_board_init();
/* enable interupts */
enable_irq();
uart_output_init();
if (TRUE == ethIf_init(mac)) {
uart_output("MAC initialized\r\n");
}
else {
uart_output("Failed to initialized MAC controller\r\n");
}
while(1)
{
UNS_16 len = 0;
len = ethIf_poll(inBuf, INBUF_LEN);
if(len > 0)
{
ethInput(inBuf, len);
}
}
}
/**********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
*********************************************************************/
void c_entry(void)
{
SWIM_WINDOW_T win1;
COLOR_T clr, *fblog;
int idx;
INT_32 lcddev;
UNS_16 xgs, ygs, curx, cury, curym, xidx;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Setup miscellaneous board functions */
phy3250_board_init();
/* Setup LCD muxing for STN Color 16BPP */
clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1);
/* Enable clock to LCD block (HCLK_EN)*/
clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1);
/* Setup LCD paramaters in the LCD controller */
lcddev = lcd_open(CLCDC, (INT_32) &LCD_DISPLAY);
/* Upper Panel Frame Base Address register */
lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF);
/* Enable LCD controller and power signals */
lcd_ioctl(lcddev, LCD_PWENABLE, 1);
/* Enable LCD backlight */
phy3250_lcd_backlight_enable(TRUE);
/* Enable LCD power */
phy3250_lcd_power_enable(TRUE);
/* Set frame buffer address */
fblog = (COLOR_T *)
cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF);
/* Create a SWIM window */
swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,
LCD_DISPLAY.lines_per_panel, fblog, 0, 0,
(LCD_DISPLAY.pixels_per_line - 1),
(LCD_DISPLAY.lines_per_panel - 1),1, WHITE, BLACK, BLACK);
/* Compute vertical size for bars */
ygs = LCD_DISPLAY.lines_per_panel / 3;
/* Draw Red bars */
cury = 0;
curx = 0;
curym = ygs - 1;
xgs = LCD_DISPLAY.pixels_per_line / RED_COLORS;
clr = BLACK;
for (xidx = 0; xidx < RED_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0800;
}
/* Draw green bars */
cury = cury + ygs;
curx = 0;
curym = cury + (ygs - 1);
xgs = LCD_DISPLAY.pixels_per_line / GREEN_COLORS;
clr = BLACK;
for (xidx = 0; xidx < GREEN_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0020;
}
/* Draw blue bars */
cury = cury + ygs;
curx = 0;
curym = cury + (ygs - 1);
xgs = LCD_DISPLAY.pixels_per_line / BLUE_COLORS;
clr = BLACK;
for (xidx = 0; xidx < BLUE_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0001;
}
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
SWIM_WINDOW_T win1;
COLOR_T *fblog;
INT_32 lcddev;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Setup miscellaneous board functions */
phy3250_board_init();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install RTC interrupt handler as a IRQ interrupts */
int_install_irq_handler(IRQ_RTC, (PFV) rtc_user_interrupt);
/* Open RTC */
rtcdev = rtc_open(RTC, 0);
if (rtcdev == 0)
{
/* Error */
return -1;
}
/* Set a 1s match rate */
secs = lsecs = 0;
mstp.match_num = 0;
mstp.use_match_int = TRUE;
mstp.enable_onsw = FALSE;
mstp.match_tick_val = secs + 1;
rtc_ioctl(rtcdev, RTC_ENABLE, 0);
rtc_ioctl(rtcdev, RTC_SET_COUNT, 0);
rtc_ioctl(rtcdev, RTC_CLEAR_INTS, RTC_MATCH0_INT_STS);
rtc_ioctl(rtcdev, RTC_SETUP_MATCH, (INT_32) &mstp);
/* Setup LCD muxing for STN Color 16BPP */
clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1);
/* Enable clock to LCD block (HCLK_EN)*/
clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1);
/* Setup LCD paramaters in the LCD controller */
lcddev = lcd_open(CLCDC, (INT_32) & LCD_DISPLAY);
/* Upper Panel Frame Base Address register */
lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF);
/* Enable LCD controller and power signals */
lcd_ioctl(lcddev, LCD_PWENABLE, 1);
/* Enable LCD backlight */
phy3250_lcd_backlight_enable(TRUE);
/* Enable LCD power */
phy3250_lcd_power_enable(TRUE);
/* Set frame buffer address */
fblog = (COLOR_T *) cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF);
/* Create a SWIM window */
swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,
LCD_DISPLAY.lines_per_panel, fblog, 0, 0,
(LCD_DISPLAY.pixels_per_line - 1), (LCD_DISPLAY.lines_per_panel - 1),
1, WHITE, BLACK, BLACK);
swim_put_ltext(&win1, "RTC example: This example will print the message "
"TICK whenever an RTC interrupt occurs (1 second intervals). It will "
"quit after 10 seconds\n");
/* Enable RTC (starts counting) */
rtc_ioctl(rtcdev, RTC_ENABLE, 1);
/* Enable RTC interrupt in the interrupt controller */
int_enable(IRQ_RTC);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 10 seconds and let interrupts toggle the LEDs */
while (secs < 10)
{
if (lsecs < secs)
{
swim_put_ltext(&win1, "TICK\n");
lsecs = secs;
}
}
/* Disable RTC interrupt in the interrupt controller */
int_disable(IRQ_RTC);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Prior to closing the RTC, the ONSW key value is set. This will
allow the RTC to keep it's value across resets as long as RTC
power is maintained */
rtc_ioctl(rtcdev, RTC_SETCLR_KEY, 1);
/* Close RTC and LCD */
rtc_close(rtcdev);
lcd_close(lcddev);
return 1;
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
MST_MATCH_SETUP_T mstp;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install mstimer interrupts handlers as a IRQ interrupts */
int_install_irq_handler(IRQ_MSTIMER, (PFV) mstimer_user_interrupt);
/* Open mstimer */
mstimerdev = mstimer_open(MSTIMER, 0);
if (mstimerdev == 0)
{
/* Error */
return -1;
}
/* Set a 10mS match rate */
mstp.timer_num = 0;
mstp.use_int = TRUE;
mstp.stop_on_match = FALSE;
mstp.reset_on_match = TRUE;
mstp.tick_val = 0;
mstp.ms_val = MSTICKRATE;
mstimer_ioctl(mstimerdev, MST_CLEAR_INT, 0);
mstimer_ioctl(mstimerdev, MST_TMR_SETUP_MATCH, (INT_32) &mstp);
/* Reset terminal count */
mstimer_ioctl(mstimerdev, MST_TMR_RESET, 0);
/* Enable mstimer (starts counting) */
msecs = 0;
mstimer_ioctl(mstimerdev, MST_TMR_ENABLE, 1);
/* Enable mstimer interrupts in the interrupt controller */
int_enable(IRQ_MSTIMER);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 10 seconds and let interrupts toggle the LEDs */
while (msecs < MSTIMEOUT);
/* Disable mstimer interrupts in the interrupt controller */
int_disable(IRQ_MSTIMER);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Close mstimer */
mstimer_close(mstimerdev);
return 1;
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Setup miscellaneous board functions */
phy3250_board_init();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Enable simple WDT clock */
clkpwr_clk_en_dis(CLKPWR_WDOG_CLK, 1);
/* Install WDT interrupt handler as an IRQ interrupt */
int_install_ext_irq_handler(IRQ_WATCH,
(PFV) wdt_user_interrupt, ACTIVE_HIGH, 1);
/* Open WDT */
wdtdev = wdt_open(WDT, 0);
if (wdtdev == 0)
{
/* Error */
return -1;
}
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Drive RESETOUT high/low/high using RESFRC1 */
wdtsetup.initial_setup = TRUE;
wdtsetup.pause = 1;
wdtsetup.resfrc2 = 0;
wdtsetup.resfrc1 = 0;
wdtsetup.m_res2 = 0;
wdtsetup.m_res1 = 0;
wdtsetup.ext_match_setup = WDT_EXT_MATCH_IDLE;
wdtsetup.match_setup = WDT_MATCH_IDLE;
wdtsetup.match0_update = FALSE;
wdtsetup.counter_update = FALSE;
wdtsetup.pulse_update = FALSE;
wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup);
delay(10000);
wdtsetup.resfrc1 = 1;
wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup);
delay(10000);
wdtsetup.resfrc1 = 0;
wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup);
delay(10000);
#ifdef RESET_CHIP_example
/* generate a 10 ms delay followed by a 3 ms */
/* RESETOUT pulse using M_RES2 = 1 */
wdt_ioctl(wdtdev, WDT_TIMER_STOP, 0);
wdt_ioctl(wdtdev, WDT_INT_DISABLE, 0);
wdt_ioctl(wdtdev, WDT_INT_CLEAR, 0);
wdtsetup.initial_setup = TRUE;
wdtsetup.pause = 1;
wdtsetup.resfrc2 = 0;
wdtsetup.resfrc1 = 0;
wdtsetup.m_res2 = 1;
wdtsetup.m_res1 = 0;
wdtsetup.ext_match_setup = WDT_EXT_MATCH_HIGH;
wdtsetup.match_setup = WDT_MATCH_EN_INT_RESET;
wdtsetup.match0 = 10 * 13000;
wdtsetup.match0_update = TRUE;
wdtsetup.counter_update = FALSE;
wdtsetup.pulse = 3 * 13000 - 5;
wdtsetup.pulse_update = TRUE;
wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup);
wdt_ioctl(wdtdev, WDT_INT_CLEAR, 0);
wdt_ioctl(wdtdev, WDT_INT_ENABLE, 0);
int_enable(IRQ_WATCH);
while (1);
#endif
/* Close WDT */
wdt_close(wdtdev);
return 1;
}
/**********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
*********************************************************************/
void c_entry(void)
{
SWIM_WINDOW_T win1;
COLOR_T clr, *fblog;
int idx;
UNS_16 xgs, ygs, curx, cury, curym, xidx;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Setup miscellaneous board functions */
phy3250_board_init();
/* enable clock to ADC block - 32KHz clock */
clkpwr_clk_en_dis(CLKPWR_ADC_CLK,1);
/* TSC IRQ goes active when the FIFO reaches the Interrupt level */
int_install_irq_handler(IRQ_TS_IRQ, (PFV) tsc_user_interrupt);
/* Enable interrupt */
int_enable(IRQ_TS_IRQ);
/* Open TSC, sets default timing values, fifo = 16,
resolution = 10bits */
tscdev = tsc_open(TSC, 0);
/* TSC Auto mode enable, this also sets AUTO bit */
tsc_ioctl(tscdev,TSC_AUTO_EN, 1);
/* Setup LCD muxing for STN Color 16BPP */
clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1);
/* Enable clock to LCD block (HCLK_EN)*/
clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1);
/* Setup LCD paramaters in the LCD controller */
lcddev = lcd_open(CLCDC, (INT_32) &LCD_DISPLAY);
/* Upper Panel Frame Base Address register */
lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF);
/* Enable LCD controller and power signals */
lcd_ioctl(lcddev, LCD_PWENABLE, 1);
/* Enable LCD backlight */
phy3250_lcd_backlight_enable(TRUE);
/* Enable LCD power */
phy3250_lcd_power_enable(TRUE);
/* write cursor image array data to cursor image RAM */
lcd_ioctl(lcddev, LCD_CRSR_INIT_IMG, (INT_32) &cursorimage[0]);
/* enable the default cursor 0 */
lcd_ioctl(lcddev,LCD_CRSR_EN,1);
/* set the cursor X/Y position */
lcd_ioctl(lcddev, LCD_CRSR_XY, 0x0);
/* set the cursor pallette BGR value, col0*/
lcd_ioctl(lcddev, LCD_CRSR_PAL0, 0x00ff0000);
/* set the cursor pallette BGR value, col1 */
lcd_ioctl(lcddev, LCD_CRSR_PAL1, 0x000000ff);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Set frame buffer address */
fblog = (COLOR_T *)cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF);
/* Create a SWIM window */
swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,
LCD_DISPLAY.lines_per_panel, fblog, 0, 0,
(LCD_DISPLAY.pixels_per_line - 1),
(LCD_DISPLAY.lines_per_panel - 1),
1, WHITE, BLACK, BLACK);
/* Compute vertical size for bars */
ygs = LCD_DISPLAY.lines_per_panel / 3;
/* Draw Red bars */
cury = 0;
curx = 0;
curym = ygs - 1;
xgs = LCD_DISPLAY.pixels_per_line / RED_COLORS;
clr = BLACK;
for (xidx = 0; xidx < RED_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0800;
}
/* Draw green bars */
cury = cury + ygs;
curx = 0;
curym = cury + (ygs - 1);
xgs = LCD_DISPLAY.pixels_per_line / GREEN_COLORS;
clr = BLACK;
for (xidx = 0; xidx < GREEN_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0020;
}
/* Draw blue bars */
cury = cury + ygs;
curx = 0;
curym = cury + (ygs - 1);
xgs = LCD_DISPLAY.pixels_per_line / BLUE_COLORS;
clr = BLACK;
for (xidx = 0; xidx < BLUE_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0001;
}
/* lets stay here forever */
while(1);
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
TMR_PSCALE_SETUP_T pscale;
TMR_MATCH_SETUP_T msetup;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install timer interrupts handlers as a IRQ interrupts */
int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt);
int_install_irq_handler(IRQ_TIMER1, (PFV) timer1_user_interrupt);
/* Open timers - this will enable the clocks for all timers when
match control, match output, and capture control functions
disabled. Default clock will be internal. */
timer0dev = timer_open(TIMER_CNTR0, 0);
timer1dev = timer_open(TIMER_CNTR1, 0);
/******************************************************************/
/* Setup timer 0 for a 10Hz match rate */
/* Use a prescale count time of 100uS */
pscale.ps_tick_val = 0; /* Use ps_us_val value */
pscale.ps_us_val = 100; /* 100uS */
timer_ioctl(timer0dev, TMR_SETUP_PSCALE, (INT_32) &pscale);
/* Use a match count value of 1000 (1000 * 100uS = 100mS (10Hz)) */
msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */
msetup.use_match_int = TRUE; /* Generate match interrupt on match */
msetup.stop_on_match = FALSE; /* Do not stop timer on match */
msetup.reset_on_match = TRUE; /* Reset timer counter on match */
msetup.match_tick_val = 999; /* Match is when timer count is 1000 */
timer_ioctl(timer0dev, TMR_SETUP_MATCH, (INT_32) &msetup);
/* Clear any latched timer 0 interrupts and enable match
interrupt */
timer_ioctl(timer0dev, TMR_CLEAR_INTS,
(TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) |
TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) |
TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) |
TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3)));
/******************************************************************/
/******************************************************************/
/* Setup timer 1 for a 4.9Hz match rate */
/* Use a prescale count time of 100uS */
pscale.ps_tick_val = 0; /* Use ps_us_val value */
pscale.ps_us_val = 10; /* 100uS */
timer_ioctl(timer1dev, TMR_SETUP_PSCALE, (INT_32) &pscale);
/* Use a match value of 490 (490 * 100uS) */
msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */
msetup.use_match_int = TRUE; /* Generate match interrupt on match */
msetup.stop_on_match = FALSE; /* Do not stop timer on match */
msetup.reset_on_match = TRUE; /* Reset timer counter on match */
msetup.match_tick_val = 489;
timer_ioctl(timer1dev, TMR_SETUP_MATCH, (INT_32) &msetup);
/* Clear any latched timer 1 interrupts and enable match
interrupt */
timer_ioctl(timer1dev, TMR_CLEAR_INTS,
(TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) |
TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) |
TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) |
TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3)));
/******************************************************************/
/* Enable timers (starts counting) */
msecs = 0;
timer_ioctl(timer0dev, TMR_ENABLE, 1);
timer_ioctl(timer1dev, TMR_ENABLE, 1);
/* Enable timer interrupts in the interrupt controller */
int_enable(IRQ_TIMER0);
int_enable(IRQ_TIMER1);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 20 seconds and let interrupts toggle the LEDs */
while (msecs < (10 * 1000));
/* Disable timer interrupts in the interrupt controller */
int_disable(IRQ_TIMER0);
int_disable(IRQ_TIMER1);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Close timers */
timer_close(timer0dev);
timer_close(timer1dev);
return 1;
}
