__forceinline void TimeUpdate(u32 cClocks)
{
u32 dClocks = cClocks - lClocks;
// Sanity Checks:
// It's not totally uncommon for the IOP's clock to jump backwards a cycle or two, and in
// such cases we just want to ignore the TimeUpdate call.
if( dClocks > (u32)-15 ) return;
// But if for some reason our clock value seems way off base (typically due to bad dma
// timings from PCSX2), just mix out a little bit, skip the rest, and hope the ship
// "rights" itself later on.
if( dClocks > (u32)(TickInterval*SanityInterval) )
{
if(MsgToConsole()) ConLog( " * SPU2 > TimeUpdate Sanity Check (Tick Delta: %d) (PS2 Ticks: %d)\n", dClocks/TickInterval, cClocks/TickInterval );
dClocks = TickInterval * SanityInterval;
lClocks = cClocks - dClocks;
}
// Visual debug display showing all core's activity! Disabled via #define on release builds.
#ifdef __WIN32__
UpdateDebugDialog();
#endif
if( SynchMode == 1 ) // AsyncMix on
SndBuffer::UpdateTempoChangeAsyncMixing();
else TickInterval = 768; // Reset to default, in case the user hotswitched from async to something else.
//Update Mixing Progress
while(dClocks>=TickInterval)
{
if(has_to_call_irq)
{
//ConLog("* SPU2-X: Irq Called (%04x) at cycle %d.\n", Spdif.Info, Cycles);
has_to_call_irq=false;
if(_irqcallback) _irqcallback();
}
#ifndef ENABLE_NEW_IOPDMA_SPU2
//Update DMA4 interrupt delay counter
if(Cores[0].DMAICounter>0)
{
Cores[0].DMAICounter-=TickInterval;
if(Cores[0].DMAICounter<=0)
{
Cores[0].MADR=Cores[0].TADR;
Cores[0].DMAICounter=0;
if(dma4callback) dma4callback();
}
else {
Cores[0].MADR+=TickInterval<<1;
}
}
//Update DMA7 interrupt delay counter
if(Cores[1].DMAICounter>0)
{
Cores[1].DMAICounter-=TickInterval;
if(Cores[1].DMAICounter<=0)
{
Cores[1].MADR=Cores[1].TADR;
Cores[1].DMAICounter=0;
//ConLog( "* SPU2 > DMA 7 Callback! %d\n", Cycles );
if(dma7callback) dma7callback();
}
else {
Cores[1].MADR+=TickInterval<<1;
}
}
#endif
dClocks -= TickInterval;
lClocks += TickInterval;
Cycles++;
// Note: IOP does not use MMX regs, so no need to save them.
//SaveMMXRegs();
Mix();
//RestoreMMXRegs();
}
}
void __fastcall TimeUpdate(u32 cClocks)
{
u32 dClocks = cClocks-lClocks;
// [Air]: Sanity Check
// If for some reason our clock value seems way off base, just mix
// out a little bit, skip the rest, and hope the ship "rights" itself later on.
if( dClocks > TickInterval*SanityInterval )
{
ConLog( " * SPU2 > TimeUpdate Sanity Check (Tick Delta: %d) (PS2 Ticks: %d)\n", dClocks/TickInterval, cClocks/TickInterval );
dClocks = TickInterval*SanityInterval;
lClocks = cClocks-dClocks;
}
//UpdateDebugDialog();
//Update Mixing Progress
while(dClocks>=TickInterval)
{
if(has_to_call_irq)
{
ConLog(" * SPU2: Irq Called (%04x).\n",Spdif.Info);
has_to_call_irq=false;
if(_irqcallback) _irqcallback();
}
if(Cores[0].InitDelay>0)
{
Cores[0].InitDelay--;
if(Cores[0].InitDelay==0)
{
Cores[0].Reset();
}
}
if(Cores[1].InitDelay>0)
{
Cores[1].InitDelay--;
if(Cores[1].InitDelay==0)
{
Cores[1].Reset();
}
}
//Update DMA4 interrupt delay counter
if(Cores[0].DMAICounter>0)
{
Cores[0].DMAICounter-=TickInterval;
if(Cores[0].DMAICounter<=0)
{
Cores[0].MADR=Cores[0].TADR;
Cores[0].DMAICounter=0;
if(dma4callback) dma4callback();
}
else {
Cores[0].MADR+=TickInterval<<1;
}
}
//Update DMA7 interrupt delay counter
if(Cores[1].DMAICounter>0)
{
Cores[1].DMAICounter-=TickInterval;
if(Cores[1].DMAICounter<=0)
{
Cores[1].MADR=Cores[1].TADR;
Cores[1].DMAICounter=0;
//ConLog( "* SPU2 > DMA 7 Callback! %d\n", Cycles );
if(dma7callback) dma7callback();
}
else {
Cores[1].MADR+=TickInterval<<1;
}
}
dClocks-=TickInterval;
lClocks+=TickInterval;
Cycles++;
Mix();
}
}
