/**
* @brief UART de-initialization.
*
* @param[in] uartp pointer to the @p UARTDriver object
*/
static void uart_stop(UARTDriver *uartp)
{
/* Stops RX and TX DMA channels.*/
dmaChannelDisable(uartp->dmarxnr);
dmaChannelDisable(uartp->dmatxnr);
/* Stops USART operations.*/
HWREG(uartp->uart + UART_O_CTL) &= ~UART_CTL_UARTEN;
}
/**
* @brief Starts a receive operation on the UART peripheral.
* @note The buffers are organized as uint8_t arrays for data sizes below
* or equal to 8 bits else it is organized as uint16_t arrays.
*
* @param[in] uartp pointer to the @p UARTDriver object
* @param[in] n number of data frames to send
* @param[out] rxbuf the pointer to the receive buffer
*
* @notapi
*/
void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
/* TODO: This assert should be moved to the dma helper driver */
osalDbgAssert((uint32_t)rxbuf >= SRAM_BASE, "rxbuf should be in SRAM region.");
dmaChannelDisable(uartp->dmarxnr);
/* Configure for 8-bit transfers.*/
primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR);
primary[uartp->dmarxnr].dstendp = (volatile void *)rxbuf+n-1;
primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(n) |
UDMA_CHCTL_XFERMODE_BASIC;
dmaChannelSingleBurst(uartp->dmarxnr);
dmaChannelPrimary(uartp->dmarxnr);
dmaChannelPriorityDefault(uartp->dmarxnr);
dmaChannelEnableRequest(uartp->dmarxnr);
/* Enable DMA channel, transfer starts immediately.*/
dmaChannelEnable(uartp->dmarxnr);
}
void dac_lld_stop_conversion(DACDriver *dacp) {
/* If in active state then disables the DAC.*/
if (dacp->state == DAC_ACTIVE) {
/* DMA disable.*/
dmaChannelDisable(LPC17xx_DAC_DMA_CHANNEL);
}
};
/**
* @brief Shared end-of-rx service routine.
*
* @param[in] spip pointer to the @p SPIDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
/* DMA errors handling.*/
#if defined(SAMA_SPI_DMA_ERROR_HOOK)
if ((flags & (XDMAC_CIS_RBEIS | XDMAC_CIS_ROIS)) != 0) {
SAMA_SPI_DMA_ERROR_HOOK(spip);
}
#else
(void)flags;
#endif
/* Stop everything.*/
dmaChannelDisable(spip->dmatx);
dmaChannelDisable(spip->dmarx);
/* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/
_spi_isr_code(spip);
}
/**
* @brief Stops any ongoing transmission.
* @note Stopping a transmission also suppresses the transmission callbacks.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @return The number of data frames not transmitted by the
* stopped transmit operation.
*
* @notapi
*/
size_t uart_lld_stop_send(UARTDriver *uartp)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
uint16_t left;
dmaChannelDisable(uartp->dmatxnr);
left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4;
return left;
}
/**
* @brief Deactivates the DAC peripheral.
*
* @param[in] dacp pointer to the @p DACDriver object
*
* @notapi
*/
void dac_lld_stop(DACDriver *dacp) {
/* If in ready state then disables the DAC clock.*/
if (dacp->state == DAC_READY) {
/* DMA disable.*/
dmaChannelDisable(LPC17xx_DAC_DMA_CHANNEL);
dmaChannelRelease(LPC17xx_DAC_DMA_CHANNEL);
/* Disable DAC */
LPC_PINCON->PINSEL1 &= ~(2UL << 20); /* Disable AOUT P0.26 pin.*/
}
}
/**
* @brief Shared end-of-tx service routine.
*
* @param[in] cryp pointer to the @p CRYDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void crypto_lld_serve_write_interrupt(CRYDriver *cryp, uint32_t flags) {
/* DMA errors handling.*/
#if defined(SAMA_CRY_DMA_ERROR_HOOK)
(void)cryp;
if ((flags & (XDMAC_CIS_WBEIS | XDMAC_CIS_ROIS)) != 0) {
SAMA_CRY_DMA_ERROR_HOOK(cryp);
}
#else
(void)cryp;
(void)flags;
#endif
dmaChannelDisable(cryp->dmatx);
if (cryp->rxdmamode == 0xFFFFFFFF)
_cry_isr_code(cryp);
}
/**
* @brief Shared end-of-rx service routine.
*
* @param[in] cryp pointer to the @p CRYDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void crypto_lld_serve_read_interrupt(CRYDriver *cryp, uint32_t flags) {
/* DMA errors handling.*/
#if defined(SAMA_CRY_DMA_ERROR_HOOK)
if ((flags & (XDMAC_CIS_RBEIS | XDMAC_CIS_ROIS)) != 0) {
SAMA_CRY_DMA_ERROR_HOOK(cryp);
}
#else
(void)flags;
#endif
/* D-Cache L1 is enabled */
cacheInvalidateRegion(cryp->out, cryp->len);
/* Stop everything.*/
dmaChannelDisable(cryp->dmarx);
/* Portable CRY ISR code defined in the high level driver, note, it is
a macro.*/
_cry_isr_code(cryp);
}
/**
* @brief Releases a DMA channel.
* @pre The channel must have been allocated using @p dmaChannelAllocate().
* @post The channel is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmachp pointer to a sama_dma_channel_t structure
*
* @special
*/
void dmaChannelRelease(sama_dma_channel_t *dmachp) {
osalDbgCheck(dmachp != NULL);
/* Check if the channel is free.*/
osalDbgAssert(dmachp->state != SAMA_DMA_FREE,
"not allocated");
/* Disables channel */
dmaChannelDisable(dmachp);
/* Disables interrupt */
(dmachp)->xdmac->XDMAC_GID = XDMAC_GID_ID0 << ((dmachp)->chid);
/* Clear dma descriptor */
(dmachp)->xdmac->XDMAC_CHID[((dmachp)->chid)].XDMAC_CNDA = 0;
(dmachp)->xdmac->XDMAC_CHID[((dmachp)->chid)].XDMAC_CNDC = 0;
/* Marks the stream as not allocated.*/
(dmachp)->state = SAMA_DMA_FREE;
}
/**
* @brief Puts the receiver in the UART_RX_IDLE state.
*
* @param[in] uartp pointer to the @p UARTDriver object
*/
static void uart_enter_rx_idle_loop(UARTDriver *uartp)
{
tiva_udma_table_entry_t *primary = udmaControlTable.primary;
dmaChannelDisable(uartp->dmarxnr);
/* Configure for 8-bit transfers.*/
primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR);
primary[uartp->dmarxnr].dstendp = (volatile void *)&uartp->rxbuf;
primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
UDMA_CHCTL_ARBSIZE_4 |
UDMA_CHCTL_XFERSIZE(1) |
UDMA_CHCTL_XFERMODE_BASIC;
dmaChannelSingleBurst(uartp->dmarxnr);
dmaChannelPrimary(uartp->dmarxnr);
dmaChannelPriorityDefault(uartp->dmarxnr);
dmaChannelEnableRequest(uartp->dmarxnr);
/* Enable DMA channel, transfer starts immediately.*/
dmaChannelEnable(uartp->dmarxnr);
}