const struct spi_comm_packet *spi_master_wait_response_done(void)
{
const struct spi_comm_packet *resp =
(const struct spi_comm_packet *)in_msg;
stm32_spi_regs_t *spi = STM32_SPI1_REGS;
if (dma_wait(STM32_DMAC_SPI1_TX) || dma_wait(STM32_DMAC_SPI1_RX)) {
debug_printf("SPI: Incomplete response\n");
goto err_wait_response_done;
}
if (spi->sr & STM32_SPI_SR_CRCERR) {
debug_printf("SPI: CRC mismatch\n");
goto err_wait_response_done;
}
if (resp->cmd_sts != EC_SUCCESS) {
debug_printf("SPI: Slave error\n");
goto err_wait_response_done;
}
exit_wait_response_done:
dma_disable(STM32_DMAC_SPI1_TX);
dma_disable(STM32_DMAC_SPI1_RX);
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
/* Set CS1 (slave SPI_NSS) to high */
STM32_GPIO_BSRR(GPIO_A) = 1 << 6;
return resp;
err_wait_response_done:
resp = NULL;
goto exit_wait_response_done;
}
int spi_slave_send_response_flush(void)
{
int ret;
ret = dma_wait(STM32_DMAC_SPI1_TX);
ret |= dma_wait(STM32_DMAC_SPI1_RX);
dma_disable(STM32_DMAC_SPI1_TX);
dma_disable(STM32_DMAC_SPI1_RX);
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
/* Set N_CHG (master SPI_NSS) to low */
STM32_GPIO_BSRR(GPIO_A) = 1 << (1 + 16);
return ret;
}
static int spi_master_read_write_byte(uint8_t *in_buf, uint8_t *out_buf, int sz)
{
int ret;
dma_start_rx(&dma_rx_option, sz, in_buf);
dma_prepare_tx(&dma_tx_option, sz, out_buf);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
ret = dma_wait(STM32_DMAC_SPI1_TX);
ret |= dma_wait(STM32_DMAC_SPI1_RX);
dma_disable(STM32_DMAC_SPI1_TX);
dma_disable(STM32_DMAC_SPI1_RX);
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
return ret;
}
int adc_read_all_channels(int *data)
{
int i;
uint32_t channels = 0;
uint32_t raw_data[ADC_CH_COUNT];
const struct adc_t *adc;
int restore_watchdog = 0;
int ret = EC_SUCCESS;
mutex_lock(&adc_lock);
if (adc_watchdog_enabled()) {
restore_watchdog = 1;
adc_disable_watchdog_no_lock();
}
/* Select all used channels */
for (i = 0; i < ADC_CH_COUNT; ++i)
channels |= 1 << adc_channels[i].channel;
STM32_ADC_CHSELR = channels;
/* Enable DMA */
STM32_ADC_CFGR1 |= 0x1;
dma_clear_isr(STM32_DMAC_ADC);
dma_start_rx(&dma_adc_option, ADC_CH_COUNT, raw_data);
/* Clear flags */
STM32_ADC_ISR = 0xe;
STM32_ADC_CR |= 1 << 2; /* ADSTART */
if (dma_wait(STM32_DMAC_ADC)) {
ret = EC_ERROR_UNKNOWN;
goto fail; /* goto fail; goto fail; */
}
for (i = 0; i < ADC_CH_COUNT; ++i) {
adc = adc_channels + i;
data[i] = (raw_data[i] & 0xffff) *
adc->factor_mul / adc->factor_div + adc->shift;
}
fail:
if (restore_watchdog)
adc_enable_watchdog_no_lock();
mutex_unlock(&adc_lock);
return ret;
}
void optimsoc_dma_transfer(void *local, uint32_t remote_tile, void *remote,
size_t size, dma_direction_t dir)
{
dma_transfer_handle_t dma_handle;
/* allocate transfer handle */
while(dma_alloc(&dma_handle) != DMA_SUCCESS) {
optimsoc_thread_yield(optimsoc_thread_current());
}
assert(size % 4 == 0);
dma_transfer(local, remote_tile, remote, size/4, dir, dma_handle);
dma_wait(dma_handle);
dma_free(dma_handle);
}
void dma_flush(void)
{
// TODO: queue these flush requests
// Wait until finished
dma_wait();
// Check if we even have a second block
if(dma_run == dma_end-1)
return;
// Send DMA data
DMA_n_MADR(2) = 0x00FFFFFF & (uint32_t)&dma_queue[dma_run];
DMA_n_CHCR(2) |= 0x01000000;
// Create new block
dma_init_block();
}
int adc_read_all_channels(int *data)
{
int i;
int16_t raw_data[ADC_CH_COUNT];
const struct adc_t *adc;
int restore_watchdog = 0;
int ret = EC_SUCCESS;
if (!adc_powered())
return EC_ERROR_UNKNOWN;
mutex_lock(&adc_lock);
if (adc_watchdog_enabled()) {
restore_watchdog = 1;
adc_disable_watchdog_no_lock();
}
adc_configure_all();
dma_clear_isr(STM32_DMAC_ADC);
dma_start_rx(&dma_adc_option, ADC_CH_COUNT, raw_data);
/* Start conversion */
STM32_ADC_CR2 |= (1 << 0); /* ADON */
if (dma_wait(STM32_DMAC_ADC)) {
ret = EC_ERROR_UNKNOWN;
goto exit_all_channels;
}
for (i = 0; i < ADC_CH_COUNT; ++i) {
adc = adc_channels + i;
data[i] = raw_data[i] * adc->factor_mul / adc->factor_div +
adc->shift;
}
exit_all_channels:
dma_disable(STM32_DMAC_ADC);
if (restore_watchdog)
adc_enable_watchdog_no_lock();
mutex_unlock(&adc_lock);
return ret;
}
static void spi_nss_interrupt(void)
{
const struct spi_comm_packet *cmd =
(const struct spi_comm_packet *)in_msg;
stm32_spi_regs_t *spi = STM32_SPI1_REGS;
if (spi->sr & STM32_SPI_SR_RXNE)
in_msg[0] = spi->dr;
master_slave_sync(5);
/* Read in the packet size */
while (!(spi->sr & STM32_SPI_SR_RXNE))
;
in_msg[0] = spi->dr;
/* Read in the rest of the packet */
dma_clear_isr(STM32_DMAC_SPI1_RX);
dma_start_rx(&dma_rx_option, in_msg[0] + SPI_PACKET_HEADER_SIZE - 1,
in_msg + 1);
dma_prepare_tx(&dma_tx_option, in_msg[0] + SPI_PACKET_HEADER_SIZE - 1,
out_msg);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
master_slave_sync(5);
if (dma_wait(STM32_DMAC_SPI1_RX) != EC_SUCCESS) {
debug_printf("SPI: Incomplete packet\n");
spi_slave_nack();
return;
}
if (spi->sr & STM32_SPI_SR_CRCERR) {
debug_printf("SPI: CRC mismatch\n");
spi_slave_nack();
return;
}
if (cmd->cmd_sts == TS_CMD_HELLO)
spi_slave_hello_back(cmd);
else if (cmd->cmd_sts == TS_CMD_FULL_SCAN)
touch_scan_slave_start();
else
spi_slave_nack();
}
static int i2c_write_raw_slave(int port, void *buf, int len)
{
stm32_dma_chan_t *chan;
int rv;
/* we don't want to race with TxE interrupt event */
disable_i2c_interrupt(port);
/* Configuring DMA1 channel DMAC_SLAVE_TX */
enable_ack(port);
chan = dma_get_channel(DMAC_SLAVE_TX);
dma_prepare_tx(dma_tx_option + port, len, buf);
/* Start the DMA */
dma_go(chan);
/* Configuring i2c to use DMA */
STM32_I2C_CR2(port) |= (1 << 11);
if (in_interrupt_context()) {
/* Poll for the transmission complete flag */
dma_wait(DMAC_SLAVE_TX);
dma_clear_isr(DMAC_SLAVE_TX);
} else {
/* Wait for the transmission complete Interrupt */
dma_enable_tc_interrupt(DMAC_SLAVE_TX);
rv = task_wait_event(DMA_TRANSFER_TIMEOUT_US);
dma_disable_tc_interrupt(DMAC_SLAVE_TX);
if (!(rv & TASK_EVENT_WAKE)) {
CPRINTS("Slave timeout, resetting i2c");
i2c_init_port(port);
}
}
dma_disable(DMAC_SLAVE_TX);
STM32_I2C_CR2(port) &= ~(1 << 11);
enable_i2c_interrupt(port);
return len;
}
int main()
{
_printstrn("--------------------------------------");
_printstrn("Configuration");
_printstrn("--------------------------------------");
_printdecn("WIDTH ", WIDTH);
_printdecn("HEIGHT ", HEIGHT);
_printdecn("ROWS_EACH_COMPUTATION_PIPE ", ROWS_EACH_COMPUTATION_PIPE);
_printdecn("ROWS_EACH_COMPUTATION_OUT_PIPE ", ROWS_EACH_COMPUTATION_OUT_PIPE);
_printstrn("--------------------------------------");
/*--- Pipe Support Data allocation*/
unsigned int nr_bands_pipe = HEIGHT / ROWS_EACH_COMPUTATION_PIPE;
unsigned int band_size_1ch = WIDTH*ROWS_EACH_COMPUTATION_PIPE*sizeof(IMG_DATATYPE);
unsigned int band_size_3ch = WIDTH*ROWS_EACH_COMPUTATION_PIPE*3*sizeof(IMG_DATATYPE);
unsigned int band_word_size_3ch = band_size_3ch / 4;
int pipe_buffID = 0;
/* Pipe Buffers for each stage */
IMG_DATATYPE *csc_in[2];
csc_in[0] = (IMG_DATATYPE *) SHMALLOC(band_size_3ch); //3ch each pixel
csc_in[1] = (IMG_DATATYPE *) SHMALLOC(band_size_3ch); //3ch each pixel
IMG_DATATYPE *cvT_in[2];
cvT_in[0] = (IMG_DATATYPE *) SHMALLOC(band_size_3ch); //3ch each pixel
cvT_in[1] = (IMG_DATATYPE *) SHMALLOC(band_size_3ch); //3ch each pixel
IMG_DATATYPE *cvM_in[2];
cvM_in[0] = (IMG_DATATYPE *) SHMALLOC(band_size_1ch); //1ch each pixel
cvM_in[1] = (IMG_DATATYPE *) SHMALLOC(band_size_1ch); //1ch each pixel
unsigned int moments[2][3] = {{0,0,0},{0,0,0}};
/*--- Out-Pipe Support Data allocation*/
unsigned int nr_bands_out = HEIGHT / ROWS_EACH_COMPUTATION_OUT_PIPE;
unsigned int band_out_size_3ch = WIDTH*ROWS_EACH_COMPUTATION_OUT_PIPE*3*sizeof(IMG_DATATYPE);
unsigned int band_out_word_size_3ch = band_out_size_3ch / 4;
/* Out-pipe Buffers */
IMG_DATATYPE *curr_frame[2];
curr_frame[0] = (IMG_DATATYPE *) SHMALLOC(band_out_size_3ch); //3ch each pixel
curr_frame[1] = (IMG_DATATYPE *) SHMALLOC(band_out_size_3ch); //3ch each pixel
IMG_DATATYPE *track_in[2];
track_in[0] = (IMG_DATATYPE *) SHMALLOC(band_out_size_3ch); //3ch each pixel
track_in[1] = (IMG_DATATYPE *) SHMALLOC(band_out_size_3ch); //3ch each pixel
IMG_DATATYPE *cvAdd_out[2];
cvAdd_out[0] = (IMG_DATATYPE *) SHMALLOC(band_out_size_3ch); //3ch each pixel
cvAdd_out[1] = (IMG_DATATYPE *) SHMALLOC(band_out_size_3ch); //3ch each pixel
#ifdef APP_VERBOSE
_printstrn("--------------------------------------");
_printstrn("Buffers");
_printstrn("--------------------------------------");
_printhexp("csc_in[0] @", csc_in[0]);
_printhexp("csc_in[1] @", csc_in[1]);
_printhexp("cvT_in[0] @", cvT_in[0]);
_printhexp("cvT_in[1] @", cvT_in[1]);
_printhexp("cvM_in[0] @", cvM_in[0]);
_printhexp("cvM_in[1] @", cvM_in[1]);
_printhexp("curr_frame[0] @", curr_frame[0]);
_printhexp("curr_frame[1] @", curr_frame[1]);
_printhexp("track_in[0] @", track_in[0]);
_printhexp("track_in[1] @", track_in[1]);
_printhexp("cvAdd_out[0] @", cvAdd_out[0]);
_printhexp("cvAdd_out[1] @", cvAdd_out[1]);
_printstrn("--------------------------------------");
#endif
unsigned int caching = 0;
for(caching = 0; caching < 2; ++caching)
{
/*--- COMPUTE INPUT FRAMES --- */
#pragma omp parallel num_threads(4) firstprivate(pipe_buffID)
{
int tile_id = 0;
int proc_id = get_proc_id()-1;
int i = 0;
for(i = 0; i < NR_FRAMES; ++i)
{
/*NOTE if library supports multiple ws here you can use sections nowait */
#ifdef SINGLE_WS
#pragma omp master
#else
#pragma omp single nowait
#endif
{
_printdecp("[ColorTracking] Start computation of frame nr ", i);
//_tstamp();
}
/*NOTE if library supports multiple ws here you can use sections nowait */
#ifdef SINGLE_WS
#pragma omp sections
#else
#pragma omp sections nowait
#endif
{
/*--- DMA+CSC SECTION ---*/
#pragma omp section
{
// #ifdef APP_DEBUG
_printdecp("[CSC] operated by proc ", proc_id);
//_tstamp();
// #endif
/* DMA Events */
unsigned char pipe_job_id_read[2];
/*Current Frame*/
IMG_DATATYPE *current_frame_in = in_frame[i];
/*First DMA INLOAD */
pipe_job_id_read[pipe_buffID] = dma_prog(proc_id, /*tile_id,*/ (unsigned int) current_frame_in, (unsigned int) csc_in[pipe_buffID], band_word_size_3ch, 1, 0, 0, 1);
#pragma omp parallel num_threads(4) firstprivate(pipe_buffID)
{
unsigned int ii = 0;
for(ii = 0; ii < nr_bands_pipe; ++ii)
{
if (pipe_buffID == 0)
pipe_buffID = 1;
else
pipe_buffID = 0;
/* --------- DMA Stage --------- */
/*NOTE This in MPARM MUST be managed via master-barrier.
Single is possible to use due DMA policy.
Who program dma must be the same processor who collect dma_wait.
*/
#pragma omp master
{
/*prog next buff*/
if ((ii+1) < nr_bands_pipe)
pipe_job_id_read[pipe_buffID] = dma_prog(proc_id, /*tile_id,*/ (unsigned int) ¤t_frame_in[(ii+1)*band_size_3ch], (unsigned int) csc_in[pipe_buffID], band_word_size_3ch, 1, 0, 0, 1);
#ifdef DMA_WAIT_TIME
//_tstamp();
#endif
//Wait for DMA end
dma_wait(/*tile_id,*/ pipe_job_id_read[!pipe_buffID]);
#ifdef DMA_WAIT_TIME
//_tstamp();
#endif
}
#pragma omp barrier
/* --------- CSC Computation --------- */
#ifdef APP_VERBOSE
_printdecp("[CSC] WORKING BAND NR ", ii);
#endif
__CSC(csc_in[!pipe_buffID], cvT_in[!pipe_buffID], band_size_3ch);
#ifdef APP_VERBOSE
_printstrp("[CSC] WORKING...DONE");
#endif
/* --------- Synch to CVT --------- */
/*NOTE if library supports multiple ws here you can use single nowait */
#ifdef SINGLE_WS
#pragma omp master
#else
#pragma omp single nowait
#endif
{
#ifdef APP_VERBOSE
_printdecp("[CSC] WAITING FOR CVT @ ",!pipe_buffID);
#endif
while(!READY_FLAG_CVT[!pipe_buffID]);
READY_FLAG_CVT[!pipe_buffID] = 0;
#ifdef APP_VERBOSE
_printdecp("[CSC] RELEASE CVT @ ",!pipe_buffID);
#endif
RELEASE_FLAG_CVT[!pipe_buffID] = 1;
}
}
}//end inner parallel
// #ifdef APP_VERBOSE
_printdecp("[CSC] end computation of frame nr ", i);
// #endif
}//end section DMA+CSC
/*--- cvThreshold SECTION ---*/
#pragma omp section
{
// #ifdef APP_DEBUG
_printdecp("[CVT] operated by proc ", proc_id);
//_tstamp();
// #endif
#pragma omp parallel num_threads(4) firstprivate(pipe_buffID)
{
unsigned int ii = 0;
for(ii = 0; ii < nr_bands_pipe; ++ii)
{
/* --------- Buffer Swap --------- */
if (pipe_buffID == 0)
pipe_buffID = 1;
else
pipe_buffID = 0;
#pragma omp single
{
/* --------- Synch from CSC --------- */
READY_FLAG_CVT[!pipe_buffID] = 1;
#ifdef APP_VERBOSE
_printdecp("[CVT] WAITING FOR RELEASE @ ",!pipe_buffID);
#endif
while(!RELEASE_FLAG_CVT[!pipe_buffID]);
#ifdef APP_VERBOSE
_printdecp("[CVT] RELEASED @ ",!pipe_buffID);
#endif
RELEASE_FLAG_CVT[!pipe_buffID] = 0;
}
/* --------- cvThreshold computation --------- */
#ifdef APP_VERBOSE
_printdecp("[CVT] WORKING BAND NR ", ii);
#endif
__cvThreshold(cvT_in[!pipe_buffID], cvM_in[!pipe_buffID], band_size_1ch);
#ifdef APP_VERBOSE
_printstrp("[CVT] WORKING...DONE");
#endif
/* --------- Synch to CVM --------- */
/*NOTE if library supports multiple ws here you can use single nowait */
#ifdef SINGLE_WS
#pragma omp master
#else
#pragma omp single nowait
#endif
{
#ifdef APP_VERBOSE
_printdecp("[CVT] WAITING FOR CVM @ ",!pipe_buffID);
#endif
while(!READY_FLAG_CVM[!pipe_buffID]);
READY_FLAG_CVM[!pipe_buffID] = 0;
#ifdef APP_VERBOSE
_printdecp("[CVT] RELEASE CVM @ ",!pipe_buffID);
#endif
RELEASE_FLAG_CVM[!pipe_buffID] = 1;
}
}
}//end inner parallel
// #ifdef APP_VERBOSE
_printdecp("[CVT] end computation of frame nr ", i);
// #endif
}//end section Threshold
/*--- cvMoments SECTION ---*/
#pragma omp section
{
unsigned int frameBuffID = i & 0x1;
// #ifdef APP_DEBUG
_printdecp("[CVM] operated by proc ", proc_id);
//_tstamp();
// #endif
#pragma omp parallel num_threads(4) firstprivate(pipe_buffID)
{
unsigned int ii = 0;
for(ii = 0; ii < nr_bands_pipe; ++ii)
{
/* --------- Buffer Swap --------- */
if (pipe_buffID == 0)
pipe_buffID = 1;
else
pipe_buffID = 0;
#pragma omp single
{
/* --------- Synch from CVT --------- */
READY_FLAG_CVM[!pipe_buffID] = 1;
#ifdef APP_VERBOSE
_printdecp("[CVM] WAITING FOR RELEASE @ ",!pipe_buffID);
#endif
while(!RELEASE_FLAG_CVM[!pipe_buffID]);
#ifdef APP_VERBOSE
_printdecp("[CVM] RELEASED @ ",!pipe_buffID);
#endif
RELEASE_FLAG_CVM[!pipe_buffID] = 0;
}
/* --------- cvMoments computation --------- */
#ifdef APP_VERBOSE
_printdecp("[CVM] WORKING BAND NR", ii);
#endif
__cvMoments(cvM_in[!pipe_buffID], moments[frameBuffID], ii*ROWS_EACH_COMPUTATION_PIPE, WIDTH, band_size_1ch);
#ifdef APP_VERBOSE
_printstrp("[CVM] WORKING...DONE");
#endif
}
}//end inner parallel
/* --------- Synch to CVA --------- */
//_tstamp();
_printdecp("[CVM] end computation of frame nr ", i);
#ifdef APP_VERBOSE
_printdecp("[CVM] WAITING FOR CVA @ ",frameBuffID);
#endif
while(!READY_FLAG_CVA[frameBuffID]);
READY_FLAG_CVA[frameBuffID] = 0;
#ifdef APP_VERBOSE
_printdecp("[CVM] RELEASE CVA @ ",frameBuffID);
#endif
RELEASE_FLAG_CVA[frameBuffID] = 1;
}//end section Moments
/*--- cvAdd SECTION ---*/
#pragma omp section
{
// #ifdef APP_DEBUG
_printdecp("[CVA] operated by proc ", proc_id);
//_tstamp();
// #endif
/* DMA Events */
unsigned char out_job_id_read[4];
unsigned char out_job_id_write[2];
int out_buffID = 0;
/*Current Frame*/
IMG_DATATYPE *current_frame_in = in_frame[i];
IMG_DATATYPE *current_frame_out = out_frame[i];
unsigned int frameBuffID = i & 0x1;
/* --------- Synch from CVM --------- */
#ifdef APP_VERBOSE
_printdecp("[CVA] WAITING FOR RELEASE @ ",frameBuffID);
#endif
READY_FLAG_CVA[frameBuffID] = 1;
while(!RELEASE_FLAG_CVA[frameBuffID]);
#ifdef APP_VERBOSE
_printdecp("[CVA] RELEASED @ ",frameBuffID);
#endif
RELEASE_FLAG_CVA[frameBuffID] = 0;
/*First DMA INLOAD */
out_job_id_read[out_buffID] = dma_prog(proc_id, /*tile_id,*/ (unsigned int) current_frame_in, (unsigned int)curr_frame[out_buffID], band_out_word_size_3ch, 1, 0, 0, 1);
out_job_id_read[out_buffID+2] = dma_prog(proc_id, /*tile_id,*/ (unsigned int) track_frame, (unsigned int)track_in[out_buffID], band_out_word_size_3ch, 1, 0, 0, 1);
/* --------- cvLine --------- */
/*compute current center of gravity*/
double moment10 = moments[frameBuffID][2];
double moment01 = moments[frameBuffID][1];
double area = moments[frameBuffID][0];
double posX = moment10/area;
double posY = moment01/area;
// #ifdef APP_DEBUG
_printdecp("[CVA] area:" , moments[frameBuffID][0]);
_printdecp("[CVA] moment01:" , moments[frameBuffID][1]);
_printdecp("[CVA] moment10:" , moments[frameBuffID][2]);
_printdecp("[CVA] posX:" , posX); //NOTE TO CHECK RESULTS-> MUST BE ALWAYS 238
_printdecp("[CVA] posY:" , posY); //NOTE TO CHECK RESULTS-> MUST BE ALWAYS 62
// #endif
moments[frameBuffID][0] = moments[frameBuffID][1] = moments[frameBuffID][2] = 0;
#pragma omp parallel num_threads(4) firstprivate(out_buffID)
{
unsigned int ii;
for(ii = 0; ii < nr_bands_out; ++ii )
{
if (out_buffID == 0)
out_buffID = 1;
else
out_buffID = 0;
/* --------- DMA Stage --------- */
/*NOTE This in MPARM MUST be managed via master-barrier.
Single is possible to use due DMA policy.
Who program dma must be the same processor who collect dma_wait.
*/
#pragma omp master
{
if ((ii+1) < nr_bands_out)
{
out_job_id_read[out_buffID] = dma_prog(proc_id, /*tile_id,*/ (unsigned int)¤t_frame_in[(ii+1)*band_out_size_3ch], (unsigned int)curr_frame[out_buffID], band_out_word_size_3ch, 1, 0, 0, 1);
out_job_id_read[out_buffID+2] = dma_prog(proc_id, /*tile_id,*/ (unsigned int)&track_frame[(ii+1)*band_out_size_3ch], (unsigned int)track_in[out_buffID], band_out_word_size_3ch, 1, 0, 0, 1);
}
#ifdef DMA_WAIT_TIME
//_tstamp();
#endif
//Wait for DMA end
dma_wait(/*tile_id,*/ out_job_id_read[!out_buffID]);
dma_wait(/*tile_id,*/ out_job_id_read[(!out_buffID) + 2]);
#ifdef DMA_WAIT_TIME
//_tstamp();
#endif
}
#pragma omp barrier
/*NOTE:MISSING --------- cvLine stage --------- */
//__cvLine(track_in, posX, posY);
/* --------- cvAdd stage --------- */
#ifdef APP_VERBOSE
_printdecp("[CVA] WORKING BAND NR ", ii);
#endif
__cvAdd(curr_frame[!out_buffID], track_in[!out_buffID], cvAdd_out[!out_buffID], band_out_size_3ch);
#ifdef APP_VERBOSE
_printstrp("[CVA] WORKING...DONE");
#endif
/*DMA writeback on L3*/
/*NOTE if library supports multiple ws here you can use single nowait */
#ifdef SINGLE_WS
#pragma omp master
#else
#pragma omp single nowait
#endif
{
out_job_id_write[!out_buffID] = dma_prog(proc_id, /*tile_id,*/ (unsigned int) ¤t_frame_out[ii*band_out_size_3ch], (unsigned int)cvAdd_out[!out_buffID], band_out_word_size_3ch, 0, 1, 0, 1);
}
}//end bands for
}//end inner parallel
//_tstamp();
_printdecp("[CVA] end computation of frame nr ", i);
}//end section DMA+cvAdd
}//end sections
#pragma omp master
{
//_tstamp();
_printdecp("[ColorTracking] end computation of frame nr", i);
}
}//for frame
}//parallel
}//caching
return 0;
}
