/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype;
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
u8 data;
#endif
#define NOT_EARLY 0
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
select_bus(1, CFG_I2C_SPEED); /* select bus with T2 on it */
#endif
btype = get_board_type();
mtype = get_mem_type();
display_board_info(btype);
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
if (btype == BOARD_SDP_2430_T2) {
/* Enable VMODE following voltage switching */
data = 0x24; /* set the floor voltage to 1.05v */
i2c_write(I2C_TRITON2, 0xBB, 1, &data, 1);
data = 0x38; /* set the roof voltage to 1.3V */
i2c_write(I2C_TRITON2, 0xBC, 1, &data, 1);
data = 0x0; /* set jump mode for VDD voltage transition */
i2c_write(I2C_TRITON2, 0xBD, 1, &data, 1);
data = 1; /* enable voltage scaling */
i2c_write(I2C_TRITON2, 0xBA, 1, &data, 1);
}
#endif
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
/* init other chip select and map CS1 right after CS0 */
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0=0,size1=0;
u32 mtype, btype, rev, cpu;
u8 chg_on = 0x5; /* enable charge of back up battery */
u8 vmode_on = 0x8C;
#define NOT_EARLY 0
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
btype = get_board_type();
mtype = get_mem_type();
rev = get_cpu_rev();
cpu = get_cpu_type();
display_board_info(btype);
if (btype == BOARD_H4_MENELAUS){
update_mux(btype,mtype); /* combo part on menelaus */
i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
}
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
else /* ES2 and above can remap at 32MB granularity */
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
/********************************************************
* sdrc_init() - init the sdrc chip selects CS0 and CS1
* - early init routines, called from flash or
* SRAM.
*******************************************************/
void sdrc_init(void)
{
#define EARLY_INIT 1
/* only init up first bank here */
do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
#define NOT_EARLY 0
//20101215_Peter ++
//#define DEBUG
#if defined (CONFIG_EPXX_DDR_512MB)
#define EARLY_INIT 1
#endif
//20101215_Peter --
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype;
btype = get_board_type();
mtype = get_mem_type();
#ifndef CONFIG_3430ZEBU
/* fixme... dont know why this func is crashing in ZeBu */
display_board_info(btype);
#endif
/* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
//20101215_Peter ++
#if defined (CONFIG_EPXX_DDR_512MB)
do_sdrc_init(SDRC_CS1_OSET, EARLY_INIT);
make_cs1_contiguous();
#else
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
#endif
//20101215_Peter --
}
#ifdef DEBUG
{
unsigned int reg = 0;
reg = __raw_readl(SDRC_MCFG_0);
printf("SDRC_MCFG_0: %08x\n", reg);
reg = __raw_readl(SDRC_MCFG_1);
printf("SDRC_MCFG_1: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLA_0);
__raw_writel(reg, SDRC_ACTIM_CTRLA_1);
printf("SDRC_ACTIM_CTRLA_0: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLB_0);
__raw_writel(reg, SDRC_ACTIM_CTRLB_1);
printf("SDRC_ACTIM_CTRLB_0: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLA_1);
printf("SDRC_ACTIM_CTRLA_1: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLB_1);
printf("SDRC_ACTIM_CTRLB_1: %08x\n", reg);
reg = __raw_readl(SDRC_MANUAL_0);
printf("SDRC_MANUAL_0: %08x\n", reg);
reg = __raw_readl(SDRC_MANUAL_1);
printf("SDRC_MANUAL_1: %08x\n", reg);
reg = __raw_readl(SDRC_MR_0);
printf("SDRC_MR_0: %08x\n", reg);
reg = __raw_readl(SDRC_MR_1);
printf("SDRC_MR_1: %08x\n", reg);
reg = __raw_readl(SDRC_RFR_CTRL_0);
__raw_writel(reg, SDRC_RFR_CTRL_1);
printf("SDRC_RFR_CTRL_0: %08x\n", reg);
reg = __raw_readl(SDRC_RFR_CTRL_1);
printf("SDRC_RFR_CTRL_1: %08x\n", reg);
reg = __raw_readl(CONTROL_PROG_IO0);
printf("CONTROL_PROG_IO0: %08x\n", reg);
reg = __raw_readl(CONTROL_PROG_IO1);
printf("CONTROL_PROG_IO1: %08x\n", reg);
reg = __raw_readl(SDRC_DLLA_CTRL);
printf("SDRC_DLLA_CTRL: %08x\n", reg);
}
#endif
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
