/*************************************************************************
* FUNCTION
* EINT_LISR
*
* DESCRIPTION
* Entry function of External Interrupt Service Routine
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* No return
*
* GLOBALS AFFECTE
*
*************************************************************************/
void EINT_LISR(void)
{
kal_uint8 index;
kal_uint16 status;
status = *EINT_STATUS;
// for conventional external interrupt!
for(index=0;index<EINT_MAX_CHANNEL;index++)
{
if (status & EINT_STATUS_EINT(index))
{
GPTI_StopItem(eint_sw_debounce[index].eint_sw_debounce_handle);
if ( (eint_sw_debounce[index].eint_intr_allow == KAL_FALSE) &&
(eint_sw_debounce_time_delay[index] > 0)
)
{
GPTI_StartItem(eint_sw_debounce[index].eint_sw_debounce_handle,
eint_sw_debounce_time_delay[index],
EINT_TIMER_CALLBACK,
&eint_sw_debounce[index]);
EINT_Mask(index);
}
else
{
eint_sw_debounce[index].eint_intr_allow = KAL_FALSE;
// disable interrupt
EINT_Mask(index);
ASSERT(EINT_FUNC.eint_func[index]!=NULL);
if ( EINT_FUNC.eint_func[index] )
{
EINT_FUNC.eint_active[index] = KAL_TRUE;
drv_active_hisr(DRV_EINT_HISR_ID);
}
}
*EINT_INTACK = EINT_INTACK_EINT(index);
}
}
// for external interrupt without hardware debounce and always edge sensitive
for (index=EINT_MAX_CHANNEL; index<EINT_TOTAL_CHANNEL; index++)
{
if (status & EINT_STATUS_EINT(index))
{
EINT_Mask(index);
ASSERT(EINT_FUNC.eint_func[index]!=NULL);
if ( EINT_FUNC.eint_func[index] )
{
EINT_FUNC.eint_active[index] = KAL_TRUE;
drv_active_hisr(DRV_EINT_HISR_ID);
}
*EINT_INTACK = EINT_INTACK_EINT(index);
}
}
}
void DEINT_Process(kal_uint8 deintno)
{
kal_uint8 eintno;
eintno = gpio_get_l1_eint_src(deintno);
if ( EINT_CheckHWDebounce(eintno) )
{
if(eint_sw_debounce[eintno].eint_sw_debounce_handle != 0x7f)
{
DclSGPT_Control(eint_sw_debounce[eintno].eint_sw_debounce_handle,SGPT_CMD_STOP,0);
DclSGPT_Close(&(eint_sw_debounce[eintno].eint_sw_debounce_handle));
}
if ( (eint_sw_debounce[eintno].eint_intr_allow == KAL_FALSE) &&
(eint_sw_debounce_time_delay[eintno] > 0)
)
{
SGPT_CTRL_START_T start;
//EINT_PRINT("\tDEINT start timer, eint_sw_debounce_time_delay[index] = %d",eint_sw_debounce_time_delay[deintno]);
eint_sw_debounce[eintno].eint_sw_debounce_handle=DclSGPT_Open(DCL_GPT_CB,0);
start.u2Tick=eint_sw_debounce_time_delay[eintno];
start.pfCallback=DEINT_TIMER_CALLBACK;
start.vPara=&eint_sw_debounce[eintno];
DclSGPT_Control(eint_sw_debounce[eintno].eint_sw_debounce_handle,SGPT_CMD_START,(DCL_CTRL_DATA_T*)&start);
EINT_Mask(eintno);
}
else
{
eint_sw_debounce[eintno].eint_intr_allow = KAL_FALSE;
// disable interrupt
//EINT_PRINT("\tDEINT trigger HISR");
EINT_Mask(eintno);
ASSERT(EINT_FUNC.eint_func[eintno]!=NULL);
if ( EINT_FUNC.eint_func[eintno] )
{
EINT_FUNC.eint_active[eintno] = KAL_TRUE;
drv_active_hisr(DRV_DEINT_HISR_ID);
}
}
}
else
{
EINT_Mask(eintno);
ASSERT(EINT_FUNC.eint_func[eintno]!=NULL);
if ( EINT_FUNC.eint_func[eintno] )
{
EINT_FUNC.eint_active[eintno] = KAL_TRUE;
drv_active_hisr(DRV_DEINT_HISR_ID);
}
}
}
void hif1_lisr(void)
{
#if defined (HIF1_CHANNEL_SUPPORT)
IRQMask(IRQ_HIF_1_CODE);
#endif
//(*(volatile kal_uint32*)HIF_INTSTA_REG(1)) = 0;//hif int status,write clear
HIF_INT_CLEAR(1);
hif_internal_handle[1].DMA_BUSY = KAL_FALSE;
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepEnable(hif_sleepMode_handle[1]);//lock MD sleep mode
#endif
SLA_CustomLogging("HDM",0);//set for debug
if(hif_internal_handle[1].realtime_callback == KAL_TRUE)
{
if(hif_cb[1])
{
hif_cb[1]();
}
#if defined (HIF1_CHANNEL_SUPPORT)
IRQUnmask(IRQ_HIF_1_CODE);
#endif
}
else
drv_active_hisr((kal_uint8)DRV_HIF1_HISR_ID);
}
void idc_uart_lisr(kal_uint32 vector)
{
IRQMask(MD_IRQID_IDC2ARM);
drv_active_hisr((kal_uint8) DRV_IDC_HISR_ID);
return;
}
/*-----------------------------------------------------------------------*
*
* GPT 1us LISR function,
* pass to gpt_hw layer as a function pointer
*
*------------------------------------------------------------------------*/
DEVDRV_LS_INTSRAM_ROCODE void GPTCB_US_Lisr(kal_uint32 vector)
{
/*ASSERT( (MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER) == vector) || \
(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER) == vector) );*/
#if defined(MT6290) && defined(__ARM7EJ_S__)
IRQClearInt(vector);
#endif /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
drv_active_hisr(DRV_GPT2_HISR_ID);
}
/* USB LOGGING DSP LISR */
static void USB_LOGGING_DSP1_LISR(void)
{
IRQMask(IRQ_IRDEBUG1_CODE);
drv_active_hisr(DRV_USB_LOGGING_DSP1_HISR_ID);
#if defined(DRV_USB_LOGGING_MT50)
if (SW_SEC_0 == INT_SW_SecVersion())
{
IRQ_ResetSWRegister(IRQ_IRDEBUG1_CODE);
}
#endif
}
static void USB_LOGGING_DSP2_LISR(void)
{
IRQMask(IRQ_IRDEBUG2_CODE);
drv_active_hisr(DRV_USB_LOGGING_DSP2_HISR_ID);
}
/*************************************************************************
* FUNCTION
* EINT_LISR
*
* DESCRIPTION
* Entry function of External Interrupt Service Routine
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* No return
*
* GLOBALS AFFECTE
*
*************************************************************************/
void EINT_LISR(void)
{
kal_uint8 index;
kal_uint32 status,mask_bits;
status = EINT_L2_STA();
if (EINT_Internal_LISR_Handler(&status))
{
return;
}
// for conventional external interrupt!
for(index=0;index<EINT_TOTAL_CHANNEL;index++)
{
//EINT_PRINT("\tEINT triggered!");
if ( EINT_CheckHWDebounce(index) )
{
mask_bits = EINT_Get_Mask_Bits();
if (status & EINT_STATUS_EINT(index) && !BU_G_BIT(mask_bits, index))
{
if(eint_sw_debounce[index].eint_sw_debounce_handle != 0x7f)
{
DclSGPT_Control(eint_sw_debounce[index].eint_sw_debounce_handle,SGPT_CMD_STOP,0);
DclSGPT_Close(&(eint_sw_debounce[index].eint_sw_debounce_handle));
}
if ( (eint_sw_debounce[index].eint_intr_allow == KAL_FALSE) &&
(eint_sw_debounce_time_delay[index] > 0)
)
{
SGPT_CTRL_START_T start;
//EINT_PRINT("\tstart timer, eint_sw_debounce_time_delay[%d] = %d",index,eint_sw_debounce_time_delay[index]);
eint_sw_debounce[index].eint_sw_debounce_handle=DclSGPT_Open(DCL_GPT_CB,0);
start.u2Tick=eint_sw_debounce_time_delay[index];
start.pfCallback=EINT_TIMER_CALLBACK;
start.vPara=&eint_sw_debounce[index];
DclSGPT_Control(eint_sw_debounce[index].eint_sw_debounce_handle,SGPT_CMD_START,(DCL_CTRL_DATA_T*)&start);
EINT_Mask(index);
}
else
{
eint_sw_debounce[index].eint_intr_allow = KAL_FALSE;
// disable interrupt
EINT_Mask(index);
//EINT_PRINT("\tEINT trigger HISR");
ASSERT(EINT_FUNC.eint_func[index]!=NULL);
if ( EINT_FUNC.eint_func[index] )
{
EINT_FUNC.eint_active[index] = KAL_TRUE;
drv_active_hisr(DRV_EINT_HISR_ID);
}
}
EINT_L2_ACK(index);
}
}
else
{
mask_bits = EINT_Get_Mask_Bits();
if (status & EINT_STATUS_EINT(index) && !BU_G_BIT(mask_bits, index))
{
EINT_Mask(index);
ASSERT(EINT_FUNC.eint_func[index]!=NULL);
if ( EINT_FUNC.eint_func[index] )
{
EINT_FUNC.eint_active[index] = KAL_TRUE;
drv_active_hisr(DRV_EINT_HISR_ID);
}
EINT_L2_ACK(index);
}
}
}
}
/*
* FUNCTION
* GPTI_Callback
*
* DESCRIPTION
* GPT1 LISR
*
* CALLS
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPTI_Callback(void)
{
//kal_activate_hisr(GPTTimer.hisr);
drv_active_hisr(DRV_GPT_HISR_ID);
}
/*************************************************************************
* FUNCTION
* isrC_Main
*
* DESCRIPTION
* This function implement IRQ's LISR main dispatch routine
*
* CALLS
*
* CALL BY
* INT_IRQ_Parse()
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
#if !defined(__SSDVT_TEST__)
#if defined(MT6290) && defined(__ARM7EJ_S__)
void DEVDRV_LS_COPRO_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx)
#else /* defined(MT6290) && defined(__ARM7EJ_S__) */
void DEVDRV_LS_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx)
#endif /* else of "defined(MT6290) && defined(__ARM7EJ_S__)" */
{
#if defined(__UNIFIED_ISR_LEVEL__)
// kal_hisr processing_ehisrid;
kal_hisrid processing_hisrid;
#else /* __UNIFIED_ISR_LEVEL__ */
void *processing_lisr_backup;
kal_uint16 processing_irqx_backup;
processing_lisr_backup = processing_lisr;
processing_irqx_backup = processing_irqx;
#endif /* __UNIFIED_ISR_LEVEL__ */
processing_irqx = irqx;
processing_lisr = (void*)lisr_dispatch_tbl[irqx].lisr_handler;
processing_irqCnt++;
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
CPU_SET_CONTEXT_ID(0xaaaa0000 | ((kal_uint32)processing_irqx));
#ifdef __SWDBG_SUPPORT__
*SWDBG_MPCON = ((irqx + 0x100) << 16) | 0x8000;
#endif /* __SWDBG_SUPPORT__ */
#ifdef __WAKEUP_IRQ_DEBUG__
if (wkup_intr_log_indx != WKUP_LOG_BUF_MAX) {
wkup_intr_log_buf[wkup_intr_log_indx].irq = processing_irqx;
wkup_intr_log_indx++;
if (wkup_intr_log_indx == WKUP_LOG_BUF_MAX) {
wkup_intr_log_indx = 0;
}
}
if (wkup_timer_log_indx != WKUP_LOG_BUF_MAX) {
if (wake_tm_name != NULL) {
wkup_timer_log_buf[wkup_timer_log_indx].timer_name = wake_tm_name;
wake_tm_name = NULL;
wkup_timer_log_indx++;
if (wkup_timer_log_indx == WKUP_LOG_BUF_MAX) {
wkup_timer_log_indx = 0;
}
}
}
#endif /* __WAKEUP_IRQ_DEBUG__ */
#if defined(DEBUG_KAL) && defined(DEBUG_TIMER) && defined(__CR4__)
if(TimerHISR_State == 1)
{
GET_CURRENT_TIME(TimerHISR_Exclude_Start_Time);
TimerHISR_State = 2;
}
#endif
#if defined(__TP_SUPPORT_TIMING_CHECK__)
if(Thread_Protect_State==1)
{
Thread_Protect_State=2;
TP_Exclude_Start_Time = ust_get_current_time();
}
#endif
#ifdef __DEMAND_PAGING_PERFORMANCE_PROFILING__
demp_preempt_time_start();
#endif
#if defined(__UNIFIED_ISR_LEVEL__)
// processing_ehisrid = intrID2hisrEID[irqx];
// ASSERT(0xFF != processing_ehisrid);
// processing_hisrid = hisrid_g[processing_ehisrid];
processing_hisrid = intrID2hisrID[irqx];
if(processing_hisrid != drv_hisr)
{
EXT_ASSERT(NULL != processing_hisrid, irqx, processing_irqCnt, (kal_uint32)processing_lisr);
kal_activate_hisr(processing_hisrid);
}
else
{
drv_active_hisr(irqx);
}
/* no nested interrupt */
processing_lisr = NULL;
processing_irqx = IRQ_NOT_LISR_CONTEXT;
#else /* __UNIFIED_ISR_LEVEL__ */
ReEnableIRQ();
#if defined(__CR4__)
IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_enter_time[irqx]));
#elif defined(__MTK_MMU_V2__)
IFDEF_LISR_MEASURE_TIME(lisr_enter_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
#endif
lisr_dispatch_tbl[irqx].lisr_handler(irqx);
#if defined(__CR4__)
IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_leave_time[irqx]));
#elif defined(__MTK_MMU_V2__)
IFDEF_LISR_MEASURE_TIME(lisr_leave_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
#endif
DisableIRQ();
processing_irqx = processing_irqx_backup;
processing_lisr = processing_lisr_backup;
#endif /* __UNIFIED_ISR_LEVEL__ */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_END_CSM(0xaaaaaaaa);
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaaaaaa);
}
CPU_SET_CONTEXT_ID(0xaaaaaaaa);
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
/* Binary-coded IRQ idx */
SYS_endIsr((kal_uint8)irqx);
}
__attribute__((section ("INTSRAM_ROCODE"))) void mdci_lisr()
{
kal_uint32 arb, phy_chann, i, log_chann;
MDCI_BUFF_T *buff;
/* mask MDIF */
#if defined(MDIF_FOR_AP_SIDE)
IRQMask(IRQ_APMDIF_CODE);
#else
IRQMask(IRQ_MDIF_CODE);
#endif
/* get arbitration mode */
if (*MDIF_CON & MDIF_CON_ARB)
{
arb = 1;
}
else
{
arb = 0;
}
/* get physical channel which needs to be read */
phy_chann = *MDIF_RCHNUM;
//for (i = 0; i < MDIF_MAX_PHY; i++) {
for (i = mdci_readindx_for_MD; i < mdci_readindx_for_MD + MDIF_MAX_PHY; i++)
{
/* get logical channel one by one*/
if (phy_chann == 0) break;
i = i % MDIF_MAX_PHY;
/* get logical channel number */
if (arb == 0)
{
buff = (MDCI_BUFF_T *)MDIF_RXCHDATA + phy_chann;
log_chann = buff->channel;
i = phy_chann;
}
else if (phy_chann & (1 << i))
{
buff = (MDCI_BUFF_T *)MDIF_RXCHDATA + i;
log_chann = buff->channel;
}
else
{
continue;
}
/* validate logical channel */
if (log_chann == MDCI_FORCE_RESET_MODEM_CHANNEL)
{
#define FORCE_RESET_MODEM (0)
EXT_ASSERT(FORCE_RESET_MODEM, log_chann, phy_chann, 0);
}
else if (log_chann >= MDCI_MAX_CHANNEL)
{
EXT_ASSERT(0, log_chann, phy_chann, 0);
}
/* check state */
if (mdci_ctrl_pool[log_chann].state == MDCI_ACTIVE_READ)
{
/* use OR operation since a mdci_read() is waiting */
mdci_ctrl_pool[log_chann].state |= MDCI_ACTIVE_ISR;
}
else if (mdci_ctrl_pool[log_chann].state == MDCI_IDLE)
{
mdci_ctrl_pool[log_chann].state = MDCI_ACTIVE_ISR;
}
else if (mdci_ctrl_pool[log_chann].state == MDCI_ACTIVE_WRITE)
{
/* a mdci_write() is not finished */
EXT_ASSERT(0, phy_chann, log_chann, mdci_ctrl_pool[log_chann].state);
}
else if (mdci_ctrl_pool[log_chann].state == MDCI_ACTIVE_ISR)
{
/* a mdci_hisr() is not done yet */
if (arb == 0)
{
/* not allow in sequential mode */
EXT_ASSERT(0, phy_chann, log_chann, mdci_ctrl_pool[log_chann].state);
}
else
{
/* pend */
break; // KC: change the continue to break due to mdif phy race condition problem.
//continue;
}
}
else
{
EXT_ASSERT(0, phy_chann, log_chann, mdci_ctrl_pool[log_chann].state);
}
/* copy channel buffer */
kal_mem_cpy(&(mdci_ctrl_pool[log_chann].buff), buff, sizeof(MDCI_BUFF_T));
/* ack MDIF to release the physical channel */
*MDIF_ACK = (1 << i);
phy_chann &= ~(1<<i);
/* only one channel at one time under sequential mode */
if (arb == 0)
{
break;
}
}
mdci_readindx_for_MD = i;
#ifndef __IVP__
/* activate HISR */
if (KAL_TRUE == kal_query_systemInit())
{
#endif /* __IVP__ */
mdci_hisr();
#ifndef __IVP__
}
else
{
drv_active_hisr(DRV_MDIF_HISR_ID);
}
#endif /* __IVP__ */
}
/**
* LCD interface LISR entry
*
* @param None.
*
* @return None.
*/
void lcd_LISR(void)
{
#if (!defined(MT6205B)&&!defined(MT6208))
kal_uint32 interrupt_status;
if (DRV_Reg(DRVPDN_CON1) & DRVPDN_CON1_LCD)
{
ASSERT(0);
}
IRQMask(IRQ_LCD_CODE);
interrupt_status=DRV_Reg(LCD_INT_STATUS_REG);
#ifdef IMAGE_DATA_PATH_TIMING_ANALYSIS
if (interrupt_status & LCD_INT_STATUS_COMPLETE_BIT) {
SLA_HWLogging("LCD", SA_stop);
}
#endif
#if !defined(DRV_IDP_SUPPORT)
lcd_transfer_complete = KAL_TRUE;
drv_active_hisr(DRV_LCD_HISR_ID);
#elif defined(DRV_IDP_SUPPORT)
if (interrupt_status & LCD_INT_STATUS_COMPLETE_BIT)
{
#ifdef __SYNC_LCM_SW_SUPPORT__
if ((KAL_TRUE == sync_lcm_enable_mode) &&
(LCD_HW_CMD_QUEUE_STATE == main_lcd_operation_state) &&
(KAL_FALSE == wait_lcd_restore_config_flag)) {
lcd_cmd_latch_complete = KAL_TRUE;
} else if (KAL_TRUE == wait_lcd_restore_config_flag) {
wait_lcd_restore_config_flag=KAL_FALSE;
}
/* wait one more lcd update trigger to make sure MMI's icon/menu is updated */
#endif
lcd_transfer_complete = KAL_TRUE;
#ifdef TV_OUT_SUPPORT
/*for TVout, configure TVout buffer address and LCD memory output address*/
if (TV_OUT_OWNER_LCD == tv_output_owner)
{
kal_bool update_next_buffer = KAL_TRUE;
if (0 == tv_out_current_fb)
{
if (tv_full_screen>1) /*MMI size*/
{
if (*((volatile unsigned int *) tv_output_buffer_offset_address1)!=tv_output_replace_data)
{
if (TV_OUTPUT_MODE1 == tv_output_config_data.tv_output_mode) {
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address1);
} else if (TV_OUTPUT_MODE4 == tv_output_config_data.tv_output_mode) {
tv_output_buffer_rotate=1;
}
lcd_mem_out_address_shadow1=tv_output_buffer_offset_address2;
*((volatile unsigned int *) tv_output_buffer_offset_address2)=tv_output_replace_data;
tv_full_screen--;
}
else
update_next_buffer = KAL_FALSE;
} else {
/// back to video size
if (TV_OUTPUT_MODE1 == tv_output_config_data.tv_output_mode) {
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address1);
} else if (TV_OUTPUT_MODE4 == tv_output_config_data.tv_output_mode) {
tv_output_buffer_rotate=1;
}
lcd_mem_out_address_shadow1=main_lcd_fb_update_para.tv_output_frame_buffer2_address;
}
}
else
{
if (tv_full_screen>1)/*MMI size*/
{
if (*((volatile unsigned int *) tv_output_buffer_offset_address2)!=tv_output_replace_data)
{
if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE1)
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address2);
else if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE4)
tv_output_buffer_rotate=2;
lcd_mem_out_address_shadow1=tv_output_buffer_offset_address1;
*((volatile unsigned int *) tv_output_buffer_offset_address1)=tv_output_replace_data;
tv_full_screen--;
}
else
update_next_buffer = KAL_FALSE;
}
else/*back to video size*/
{
if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE1)
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address2);
else if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE4)
tv_output_buffer_rotate=2;
lcd_mem_out_address_shadow1=main_lcd_fb_update_para.tv_output_frame_buffer1_address;
}
}
if (KAL_TRUE == update_next_buffer)
{
tv_out_current_fb++;
tv_out_current_fb&=0x01;
tv_output_buffer_count++;
if (0xFF == tv_output_buffer_count)
{
tv_output_buffer_count=3;
}
/*When back to video size, we modify memory out addr in the HISR with ROI setting.
This can avoid video update issue(ROI and memory content are not sync) before
finishing ROI setting*/
if (tv_output_buffer_count!=2)
{
REG_LCD_ROI_WMEM_ADDR=lcd_mem_out_address_shadow1;
#ifdef __SYNC_LCM_SW_SUPPORT__
if (sync_lcm_enable_mode==KAL_TRUE)
{
if ((main_lcd_operation_state!=LCD_HW_CMD_QUEUE_STATE)||
(main_lcd_operation_state!=LCD_HW_UPDATE_SLEEP_STATE))
{
START_LCD_TRANSFER;
}
}
else
{
START_LCD_TRANSFER;
}
#else
START_LCD_TRANSFER;
#endif//__SYNC_LCM_SW_SUPPORT__
}
}
}
#endif
}
if (interrupt_status & LCD_INT_ENABLE_CMD_COMPLETE_BIT)
{
lcd_cmd_latch_complete=KAL_TRUE;
}
drv_active_hisr(DRV_LCD_HISR_ID);
#endif//DRV_IDP_SUPPORT
#endif//(!defined(MT6205B)&&!defined(MT6208))
} /* lcd_LISR() */
