/* * this sysfs is intended to retrieve two MPU addresses * needed for the INST2 utility. * the inst_log script will run this sysfs */ static ssize_t mpu_address_show(struct device *dev, struct device_attribute *attr, char *buf) { struct wmd_dev_context *dw_context = NULL; struct dev_object *hdev_obj = NULL; u32 mem_poolsize = 0; u32 GppPa = 0, DspVa = 0; u32 armPhyMemOffUncached = 0; struct dspbridge_platform_data *pdata = bridge->platform_data; hdev_obj = (struct dev_object *)drv_get_first_dev_object(); dev_get_wmd_context(hdev_obj, &dw_context); if (!dw_context) { pr_err("%s: failed to get the dev context handle\n", __func__); return 0; } GppPa = dw_context->atlb_entry[0].ul_gpp_pa; DspVa = dw_context->atlb_entry[0].ul_dsp_va; /* * the physical address offset, this offset is a * fixed value for a given platform. */ armPhyMemOffUncached = GppPa - DspVa; /* * the offset value for cached address region * on DSP address space */ mem_poolsize = pdata->phys_mempool_base - 0x20000000; /* Retrive the above calculated addresses */ return sprintf(buf, "mempoolsizeOffset 0x%x GppPaOffset 0x%x\n", mem_poolsize, armPhyMemOffUncached); }
/* * ======== pwr_wake_dsp ======== * Send command to DSP to wake it from sleep. */ int pwr_wake_dsp(const u32 timeout) { struct bridge_drv_interface *intf_fxns; struct bridge_dev_context *dw_context; int status = -EPERM; struct dev_object *hdev_obj = NULL; u32 arg = timeout; for (hdev_obj = (struct dev_object *)drv_get_first_dev_object(); hdev_obj != NULL; hdev_obj = (struct dev_object *)drv_get_next_dev_object ((u32) hdev_obj)) { if (!(dev_get_bridge_context(hdev_obj, (struct bridge_dev_context **)&dw_context))) { if (!(dev_get_intf_fxns(hdev_obj, (struct bridge_drv_interface **)&intf_fxns))) { status = (*intf_fxns->pfn_dev_cntrl) (dw_context, BRDIOCTL_WAKEUP, (void *)&arg); } } } return status; }
/* * ======== pwr_pm_post_scale======== * Sends post-notification message to DSP. */ int pwr_pm_post_scale(u16 voltage_domain, u32 level) { struct bridge_drv_interface *intf_fxns; struct bridge_dev_context *dw_context; int status = -EPERM; struct dev_object *hdev_obj = NULL; u32 arg[2]; arg[0] = voltage_domain; arg[1] = level; for (hdev_obj = (struct dev_object *)drv_get_first_dev_object(); hdev_obj != NULL; hdev_obj = (struct dev_object *)drv_get_next_dev_object ((u32) hdev_obj)) { if (!(dev_get_bridge_context(hdev_obj, (struct bridge_dev_context **)&dw_context))) { if (!(dev_get_intf_fxns(hdev_obj, (struct bridge_drv_interface **)&intf_fxns))) { status = (*intf_fxns->pfn_dev_cntrl) (dw_context, BRDIOCTL_POSTSCALE_NOTIFY, (void *)&arg); } } } return status; }
/* * ======== dev_get_first ======== * Purpose: * Retrieve the first Device Object handle from an internal linked list * DEV_OBJECTs maintained by DEV. */ struct dev_object *dev_get_first(void) { struct dev_object *dev_obj = NULL; dev_obj = (struct dev_object *)drv_get_first_dev_object(); return dev_obj; }
static void mcbsp_clk_prepare(bool flag, u8 id) { struct cfg_hostres *resources; struct dev_object *hdev_object = NULL; struct bridge_dev_context *bridge_context = NULL; u32 val; hdev_object = (struct dev_object *)drv_get_first_dev_object(); if (!hdev_object) return; dev_get_bridge_context(hdev_object, &bridge_context); if (!bridge_context) return; resources = bridge_context->resources; if (!resources) return; if (flag) { if (id == DSP_CLK_MCBSP1) { /* set MCBSP1_CLKS, on McBSP1 ON */ val = __raw_readl(resources->dw_sys_ctrl_base + 0x274); val |= 1 << 2; __raw_writel(val, resources->dw_sys_ctrl_base + 0x274); } else if (id == DSP_CLK_MCBSP2) { /* set MCBSP2_CLKS, on McBSP2 ON */ val = __raw_readl(resources->dw_sys_ctrl_base + 0x274); val |= 1 << 6; __raw_writel(val, resources->dw_sys_ctrl_base + 0x274); } } else { if (id == DSP_CLK_MCBSP1) { /* clear MCBSP1_CLKS, on McBSP1 OFF */ val = __raw_readl(resources->dw_sys_ctrl_base + 0x274); val &= ~(1 << 2); __raw_writel(val, resources->dw_sys_ctrl_base + 0x274); } else if (id == DSP_CLK_MCBSP2) { /* clear MCBSP2_CLKS, on McBSP2 OFF */ val = __raw_readl(resources->dw_sys_ctrl_base + 0x274); val &= ~(1 << 6); __raw_writel(val, resources->dw_sys_ctrl_base + 0x274); } } }
/* * ======== pwr_sleep_dsp ======== * Send command to DSP to enter sleep state. */ int pwr_sleep_dsp(const u32 sleep_code, const u32 timeout) { struct bridge_drv_interface *intf_fxns; struct bridge_dev_context *dw_context; int status = -EPERM; struct dev_object *hdev_obj = NULL; u32 ioctlcode = 0; u32 arg = timeout; for (hdev_obj = (struct dev_object *)drv_get_first_dev_object(); hdev_obj != NULL; hdev_obj = (struct dev_object *)drv_get_next_dev_object((u32) hdev_obj)) { if (dev_get_bridge_context(hdev_obj, (struct bridge_dev_context **) &dw_context)) { continue; } if (dev_get_intf_fxns(hdev_obj, (struct bridge_drv_interface **) &intf_fxns)) { continue; } if (sleep_code == PWR_DEEPSLEEP) ioctlcode = BRDIOCTL_DEEPSLEEP; else if (sleep_code == PWR_EMERGENCYDEEPSLEEP) ioctlcode = BRDIOCTL_EMERGENCYSLEEP; else status = -EINVAL; if (status != -EINVAL) { status = (*intf_fxns->pfn_dev_cntrl) (dw_context, ioctlcode, (void *)&arg); } } return status; }