/*
* Reinitialise the SerDes interface. Note that it normally powers
* up in the disabled state, so we need to explicitly activate it.
*/
static int
bge_restart_serdes(bge_t *bgep, boolean_t powerdown)
{
uint32_t macmode;
BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown));
ASSERT(mutex_owned(bgep->genlock));
/*
* Ensure that the main Ethernet MAC mode register is programmed
* appropriately for the SerDes interface ...
*/
macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
macmode |= ETHERNET_MODE_LINK_POLARITY;
macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
macmode |= ETHERNET_MODE_PORTMODE_GMII;
} else {
macmode &= ~ETHERNET_MODE_LINK_POLARITY;
macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
macmode |= ETHERNET_MODE_PORTMODE_TBI;
}
bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
/*
* Ensure that loopback is OFF and comma detection is enabled. Then
* disable the SerDes output (the first time through, it may/will
* already be disabled). If we're shutting down, leave it disabled.
*/
bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK);
bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT);
bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE);
if (powerdown)
return (DDI_SUCCESS);
/*
* Otherwise, pause, (re-)enable the SerDes output, and send
* all-zero config words in order to force autoneg restart.
* Invalidate the saved "link partners received configs", as
* we're starting over ...
*/
drv_usecwait(10000);
bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE);
bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0);
bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS);
drv_usecwait(10);
bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS);
bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR;
bgep->serdes_status = ~0U;
return (DDI_SUCCESS);
}
inline void
efe_eeprom_writebit(efe_t *efep, int bit)
{
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
drv_usecwait(EEPROM_DELAY);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS |
EECTL_EESK | (bit ? EECTL_EEDI : 0));
drv_usecwait(EEPROM_DELAY);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
drv_usecwait(EEPROM_DELAY);
}
inline int
efe_eeprom_readbit(efe_t *efep)
{
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
drv_usecwait(EEPROM_DELAY);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS |
EECTL_EESK);
drv_usecwait(EEPROM_DELAY);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
drv_usecwait(EEPROM_DELAY);
return (!!(GETCSR(efep, CSR_EECTL) & EECTL_EEDO));
}
/*
* Read the current time from the clock chip and convert to UNIX form.
* Assumes that the year in the clock chip is valid.
* Must be called with tod_lock held.
*/
static timestruc_t
todm5819_get(void)
{
int i;
timestruc_t ts;
struct rtc_t rtc;
ASSERT(MUTEX_HELD(&tod_lock));
/*
* Read from the tod, and if it isnt accessible wait
* before retrying.
*/
for (i = 0; i < TODM5819_UIP_RETRY_THRESH; i++) {
if (read_rtc(&rtc))
break;
drv_usecwait(TODM5819_UIP_WAIT_USEC);
}
if (i == TODM5819_UIP_RETRY_THRESH) {
/*
* We couldnt read from the tod
*/
tod_fault_reset();
return (hrestime);
}
DPRINTF("todm5819_get: century=%d year=%d dom=%d hrs=%d\n",
rtc.rtc_century, rtc.rtc_year, rtc.rtc_dom, rtc.rtc_hrs);
ts.tv_sec = tod_to_utc(rtc_to_tod(&rtc));
ts.tv_nsec = 0;
return (ts);
}
static void
trans_wait_panic(struct buf *cb)
{
while ((cb->b_flags & B_DONE) == 0) {
drv_usecwait(10);
}
}
void
ehc_init_pcf8584(struct ehc_envcunit *ehcp)
{
/*
* Writing PIN bit of S1 causes software reset.
* The next write to S0 will be S0' "own address".
*/
ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, EHC_S1_PIN);
/*
* Write the address which the controller chip will use
* (when addressed as a slave) on the I2C bus.
* DAF - should own address be passed as argument?
*/
ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, EHC_S0_OWN);
/*
* Writing PIN bit and ES1 bit of S1 causes software
* reset and selects the S2 register for writing.
* Now, the next write to S0 will be the S2 clock
* control register.
*/
ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1,
EHC_S1_PIN | EHC_S1_ES1);
/*
* Write the value into register that sets internal system clock
* to 12 Mhz, and the I2C bus rate (SCL) to 9 Khz.
* DAF - should these be parameters?
*/
ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0, EHC_S0_CLK);
/*
* Writing PIN bit causes software reset and the ES0 bit
* selects the (S0) register for reading/writing. The ACK
* bit being set causes controller to send ACK after each
* byte.
*/
ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1,
EHC_S1_PIN | EHC_S1_ES0 | EHC_S1_ACK);
/*
* Multi-Master: Wait for a period of time equal to the
* longest I2C message. This accounts for the case
* where multiple controllers and, if this particular one
* is "lagging", misses the BB (bus busy) condition.
* DAF - What does this need?
* We wait 200 ms since the longest transaction at this time
* on the i2c bus is a 256 byte read from the seprom which takes
* about 75 ms. Some additional buffer does no harm to the driver.
*/
drv_usecwait(EHC_LONGEST_MSG);
}
/*
* audioixp_rd97()
*
* Description:
* Get the specific AC97 Codec register.
*
* Arguments:
* void *arg The device's state structure
* uint8_t reg AC97 register number
*
* Returns:
* Register value.
*/
static uint16_t
audioixp_rd97(void *arg, uint8_t reg)
{
audioixp_state_t *statep = arg;
uint32_t value;
uint32_t result;
if (audioixp_codec_sync(statep) != DDI_SUCCESS)
return (0xffff);
value = IXP_AUDIO_OUT_PHY_PRIMARY_CODEC |
IXP_AUDIO_OUT_PHY_READ |
IXP_AUDIO_OUT_PHY_EN |
((unsigned)reg << IXP_AUDIO_OUT_PHY_ADDR_SHIFT);
PUT32(IXP_AUDIO_OUT_PHY_ADDR_DATA, value);
if (audioixp_codec_sync(statep) != DDI_SUCCESS)
return (0xffff);
for (int i = 0; i < 300; i++) {
result = GET32(IXP_AUDIO_IN_PHY_ADDR_DATA);
if (result & IXP_AUDIO_IN_PHY_READY) {
return (result >> IXP_AUDIO_IN_PHY_DATA_SHIFT);
}
drv_usecwait(10);
}
done:
audio_dev_warn(statep->adev, "time out reading codec reg %d", reg);
return (0xffff);
}
/*
* Wait until the keyboard is fully up, maybe.
* We may be the first person to talk to the keyboard, in which case
* it's patiently waiting to say "AA" to us to tell us it's up.
* In theory it sends the AA in 300ms < n < 9s, but it's a pretty
* good bet that we've already spent that long getting to that point,
* so we'll only wait long enough for the communications electronics to
* run.
*/
static void
kb8042_wait_poweron(struct kb8042 *kb8042)
{
int cnt;
int ready;
unsigned char byt;
/* wait for up to 250 ms for a response */
for (cnt = 0; cnt < 250; cnt++) {
ready = ddi_get8(kb8042->handle,
kb8042->addr + I8042_INT_INPUT_AVAIL);
if (ready != 0)
break;
drv_usecwait(1000);
}
/*
* If there's something pending, read and discard it. If not,
* assume things are OK anyway - maybe somebody else ate it
* already. (On a PC, the BIOS almost certainly did.)
*/
if (ready != 0) {
byt = ddi_get8(kb8042->handle,
kb8042->addr + I8042_INT_INPUT_DATA);
#if defined(KD_DEBUG)
if (kb8042_low_level_debug)
prom_printf(" <K:%x ", byt);
#endif
}
}
/*
* audio1575_write_ac97()
*
* Description:
* Set the specific AC97 Codec register.
*
* Arguments:
* void *arg The device's state structure
* uint8_t reg AC97 register number
* uint16_t data The data want to be set
*/
static void
audio1575_write_ac97(void *arg, uint8_t reg, uint16_t data)
{
audio1575_state_t *statep = arg;
int i;
if (audio1575_codec_sync(statep) != DDI_SUCCESS) {
return;
}
/* write the data to WRITE to the lo word of the CPR register */
PUT16(M1575_CPR_REG, data);
/* write the address to WRITE to the hi word of the CPR register */
PUT16(M1575_CPR_REG+2, reg);
/* wait until command is completed sucessfully */
for (i = 0; i < M1575_LOOP_CTR; i++) {
/* Wait for Write Ready 0x01 */
if (GET32(M1575_CSPSR_REG) & M1575_CSPSR_WRRDY) {
break;
}
drv_usecwait(1);
}
if (i < M1575_LOOP_CTR) {
(void) audio1575_read_ac97(statep, reg);
}
}
uint16_t
efe_eeprom_readw(efe_t *efep, int addrlen, uint8_t addr)
{
uint16_t val = 0;
ASSERT(addrlen > 0);
/* Write Start Bit (SB) */
efe_eeprom_writebit(efep, 1);
/* Write READ instruction */
efe_eeprom_writebit(efep, 1);
efe_eeprom_writebit(efep, 0);
/* Write EEPROM address */
for (int i = addrlen - 1; i >= 0; --i) {
efe_eeprom_writebit(efep, addr & 1U << i);
}
/* Read EEPROM word */
for (int i = EEPROM_WORDSZ - 1; i >= 0; --i) {
val |= efe_eeprom_readbit(efep) << i;
}
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE);
drv_usecwait(EEPROM_DELAY);
return (val);
}
/*ARGSUSED*/
int
plat_ide_chipreset(dev_info_t *dip, int chno)
{
uint8_t val;
int ret = DDI_SUCCESS;
if (isa_handle == NULL) {
return (DDI_FAILURE);
}
val = pci_config_get8(isa_handle, 0x58);
/*
* The dip passed as the argument is not used here.
* This will be needed for platforms which have multiple on-board SB,
* The dip passed will be used to match the corresponding ISA node.
*/
switch (chno) {
case 0:
/*
* First disable the primary channel then re-enable it.
* As per ALI no wait should be required in between have
* given 1ms delay in between to be on safer side.
* bit 2 of register 0x58 when 0 disable the channel 0.
* bit 2 of register 0x58 when 1 enables the channel 0.
*/
pci_config_put8(isa_handle, 0x58, val & 0xFB);
drv_usecwait(1000);
pci_config_put8(isa_handle, 0x58, val);
break;
case 1:
/*
* bit 3 of register 0x58 when 0 disable the channel 1.
* bit 3 of register 0x58 when 1 enables the channel 1.
*/
pci_config_put8(isa_handle, 0x58, val & 0xF7);
drv_usecwait(1000);
pci_config_put8(isa_handle, 0x58, val);
break;
default:
/*
* Unknown channel number passed. Return failure.
*/
ret = DDI_FAILURE;
}
return (ret);
}
void
sda_slot_halt(sda_slot_t *slot)
{
sda_slot_enter(slot);
slot->s_ops.so_halt(slot->s_prv);
/* We need to wait 1 msec for power down. */
drv_usecwait(1000);
sda_slot_exit(slot);
}
static int
ehc_after_read_pcf8584(struct ehc_envcunit *ehcp, uint8_t *data)
{
uint8_t discard;
uint8_t poll_status;
int i = 0;
/* set ACK in register S1 to 0 */
ddi_put8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1, EHC_S1_ES0);
/*
* Read the "byte-before-the-last-byte" - sets PIN bit to '1'
*/
*data = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0);
/* wait for completion of transmission */
do {
drv_usecwait(1000);
poll_status =
ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s1);
i++;
} while ((poll_status & EHC_S1_PIN) && i < EHC_MAX_WAIT);
if (i == EHC_MAX_WAIT) {
DCMN_ERR(CE_WARN, "ehc_after_rd_pcf8584(): read of S1 failed");
return (EHC_FAILURE);
}
if (poll_status & EHC_S1_BER) {
DCMN2_ERR(CE_WARN, "ehc_after_rd_pcf8584(): Bus error");
ehc_init_pcf8584(ehcp);
return (EHC_FAILURE);
}
if (poll_status & EHC_S1_LAB) {
DCMN2_ERR(CE_WARN, "ehc_after_rd_pcf8584(): Lost Arbitration");
ehc_init_pcf8584(ehcp);
return (EHC_FAILURE);
}
/*
* Generate the "stop" condition.
*/
ehc_stop_pcf8584(ehcp);
/*
* Read the "last" byte.
*/
discard = ddi_get8(ehcp->ctlr_handle, &ehcp->bus_ctl_regs->s0);
#ifdef lint
discard = discard;
#endif
return (EHC_SUCCESS);
}
void
sda_slot_power_off(sda_slot_t *slot)
{
sda_slot_enter(slot);
(void) sda_setprop(slot, SDA_PROP_OCR, 0);
/* XXX: FMA: on failure this should cause a fault to be generated */
/* spec requires voltage to stay low for at least 1 msec */
drv_usecwait(1000);
sda_slot_exit(slot);
}
int
efe_quiesce(dev_info_t *dip)
{
efe_t *efep = ddi_get_driver_private(dip);
PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
drv_usecwait(RESET_DELAY);
PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN);
return (DDI_SUCCESS);
}
/*
* audio1575_codec_sync()
*
* Description:
* Serialize access to the AC97 audio mixer registers.
*
* Arguments:
* audio1575_state_t *state The device's state structure
*
* Returns:
* DDI_SUCCESS Ready for an I/O access to the codec
* DDI_FAILURE An I/O access is currently in progress, can't
* perform another I/O access.
*/
static int
audio1575_codec_sync(audio1575_state_t *statep)
{
/* do the Uli Shuffle ... */
for (int i = 0; i < M1575_LOOP_CTR; i++) {
/* Read the semaphore, and loop till we own it */
if ((GET32(M1575_CASR_REG) & 1) == 0) {
for (int j = 0; j < M1575_LOOP_CTR; j++) {
/* Wait for CWRSUCC 0x8 */
if (GET32(M1575_CSPSR_REG) &
M1575_CSPSR_SUCC) {
return (DDI_SUCCESS);
}
drv_usecwait(1);
}
}
drv_usecwait(10);
}
return (DDI_FAILURE);
}
/*
* wait for the tx fifo to drain - used for urgent nowait requests
*/
void
rmc_comm_serdev_drain(struct rmc_comm_state *rcs)
{
uint8_t status;
mutex_enter(rcs->sd_state.hw_mutex);
status = sio_get_reg(rcs, SIO_LSR);
while ((status & SIO_LSR_XHRE) == 0) {
drv_usecwait(100);
status = sio_get_reg(rcs, SIO_LSR);
}
mutex_exit(rcs->sd_state.hw_mutex);
}
/*
* audioixp_reset_ac97()
*
* Description:
* Reset AC97 Codec register.
*
* Arguments:
* audioixp_state_t *state The device's state structure
*
* Returns:
* DDI_SUCCESS Reset the codec successfully
* DDI_FAILURE Failed to reset the codec
*/
static int
audioixp_reset_ac97(audioixp_state_t *statep)
{
uint32_t cmd;
int i;
CLR32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_POWER_DOWN);
drv_usecwait(10);
/* register reset */
SET32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_AC_SOFT_RESET);
/* force a read to flush caches */
(void) GET32(IXP_AUDIO_CMD);
drv_usecwait(10);
CLR32(IXP_AUDIO_CMD, IXP_AUDIO_CMD_AC_SOFT_RESET);
/* cold reset */
for (i = 0; i < 300; i++) {
cmd = GET32(IXP_AUDIO_CMD);
if (cmd & IXP_AUDIO_CMD_AC_ACTIVE) {
cmd |= IXP_AUDIO_CMD_AC_RESET | IXP_AUDIO_CMD_AC_SYNC;
PUT32(IXP_AUDIO_CMD, cmd);
return (DDI_SUCCESS);
}
cmd &= ~IXP_AUDIO_CMD_AC_RESET;
cmd |= IXP_AUDIO_CMD_AC_SYNC;
PUT32(IXP_AUDIO_CMD, cmd);
(void) GET32(IXP_AUDIO_CMD);
drv_usecwait(10);
cmd |= IXP_AUDIO_CMD_AC_RESET;
PUT32(IXP_AUDIO_CMD, cmd);
drv_usecwait(10);
}
audio_dev_warn(statep->adev, "AC'97 reset timed out");
return (DDI_FAILURE);
}
/*
* function to trigger a POST on the device
*
* dev - software handle to the device
*
*/
int
oce_POST(struct oce_dev *dev)
{
mpu_ep_semaphore_t post_status;
clock_t tmo;
clock_t earlier = ddi_get_lbolt();
/* read semaphore CSR */
post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
if (oce_fm_check_acc_handle(dev, dev->csr_handle) != DDI_FM_OK) {
ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
return (DDI_FAILURE);
}
/* if host is ready then wait for fw ready else send POST */
if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
post_status.bits.stage = POST_STAGE_CHIP_RESET;
OCE_CSR_WRITE32(dev, MPU_EP_SEMAPHORE, post_status.dw0);
if (oce_fm_check_acc_handle(dev, dev->csr_handle) !=
DDI_FM_OK) {
ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
return (DDI_FAILURE);
}
}
/* wait for FW ready */
tmo = drv_usectohz(60000000); /* 1.0min */
for (;;) {
if ((ddi_get_lbolt() - earlier) > tmo) {
tmo = 0;
break;
}
post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
if (oce_fm_check_acc_handle(dev, dev->csr_handle) !=
DDI_FM_OK) {
ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
return (DDI_FAILURE);
}
if (post_status.bits.error) {
oce_log(dev, CE_WARN, MOD_CONFIG,
"0x%x POST ERROR!!", post_status.dw0);
return (DDI_FAILURE);
}
if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
return (DDI_SUCCESS);
drv_usecwait(100);
}
return (DDI_FAILURE);
} /* oce_POST */
void
efe_reset(efe_t *efep)
{
ASSERT(mutex_owned(&efep->efe_intrlock));
ASSERT(mutex_owned(&efep->efe_txlock));
PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
drv_usecwait(RESET_DELAY);
/* Assert internal clock source (AN 7.15) */
for (int i = 0; i < RESET_TEST_CYCLES; ++i) {
PUTCSR(efep, CSR_TEST, TEST_CLOCK);
}
}
int
mii_reset_phy(mii_handle_t mac, int phy, enum mii_wait_type wait)
{
int i;
struct phydata *phyd;
ushort_t control;
if (!(phyd = mii_get_valid_phydata(mac, phy)))
return (MII_PARAM);
/* Strobe the reset bit in the control register */
mac->mii_write(mac->mii_dip, phy, MII_CONTROL,
phyd->control | MII_CONTROL_RESET);
phyd->state = phy_state_unknown;
/*
* This is likely to be very fast (ie, by the time we read the
* control register once, the devices we have seen can have already
* reset), but according to 802.3u 22.2.4.1.1, it could be up to .5 sec.
*/
if (wait == mii_wait_interrupt || wait == mii_wait_user) {
for (i = 100; i--; ) {
control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL);
if (!(control & MII_CONTROL_RESET))
break;
drv_usecwait(10);
}
if (i)
goto reset_completed;
}
if (wait == mii_wait_user) {
for (i = 50; i--; ) {
control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL);
if (!(control & MII_CONTROL_RESET))
break;
delay(drv_usectohz(10000));
}
if (i)
goto reset_completed;
return (MII_HARDFAIL); /* It MUST reset within this time */
}
return (MII_TIMEOUT);
reset_completed:
(void) mii_sync(mac, phy);
return (MII_SUCCESS);
}
/*
* Basic low-level function to reset the PHY.
* Doesn't incorporate any special-case workarounds.
*
* Returns TRUE on success, FALSE if the RESET bit doesn't clear
*/
static boolean_t
bge_phy_reset(bge_t *bgep)
{
uint16_t control;
uint_t count;
BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep));
ASSERT(mutex_owned(bgep->genlock));
if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
drv_usecwait(40);
/* put PHY into ready state */
bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
drv_usecwait(40);
}
/*
* Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
*/
bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET);
for (count = 0; ++count < 1000; ) {
drv_usecwait(5);
control = bge_mii_get16(bgep, MII_CONTROL);
if (BIC(control, MII_CONTROL_RESET))
return (B_TRUE);
}
if (DEVICE_5906_SERIES_CHIPSETS(bgep))
(void) bge_adj_volt_5906(bgep);
BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control));
return (B_FALSE);
}
int
mii_isolate(mii_handle_t mac, int phy)
{
struct phydata *phyd;
if (!(phyd = mii_get_valid_phydata(mac, phy)))
return (MII_PARAM);
phyd->control |= MII_CONTROL_ISOLATE;
mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
/* Wait for device to settle */
drv_usecwait(50);
return (MII_SUCCESS);
}
/*
* poll_port -- wait for a register to achieve a
* specific state. Arguments are a mask of bits we care about,
* and two sub-masks. To return normally, all the bits in the
* first sub-mask must be ON, all the bits in the second sub-
* mask must be OFF. If about seconds pass without the register
* achieving the desired bit configuration, we return 1, else
* 0.
*/
int
poll_port(ushort_t port, ushort_t mask, ushort_t onbits, ushort_t offbits)
{
int i;
ushort_t maskval;
for (i = 500000; i; i--) {
maskval = inb(port) & mask;
if (((maskval & onbits) == onbits) &&
((maskval & offbits) == 0))
return (0);
drv_usecwait(10);
}
return (1);
}
static int
todds1307_write_rtc(struct rtc_t *rtc)
{
ds1307_state_t *statep = NULL;
i2c_transfer_t *i2c_tp = NULL;
int i2c_cmd_status = I2C_SUCCESS;
if (!todds1307_attach_done) {
return (todds1307_prom_setdate(rtc));
}
statep = ddi_get_soft_state(ds1307_statep, instance);
if (statep == NULL) {
return (DDI_FAILURE);
}
if ((i2c_cmd_status = i2c_transfer_alloc(statep->ds1307_i2c_hdl,
&i2c_tp, 8, 0, I2C_SLEEP)) != I2C_SUCCESS) {
return (i2c_cmd_status);
}
i2c_tp->i2c_version = I2C_XFER_REV;
i2c_tp->i2c_flags = I2C_WR;
i2c_tp->i2c_wbuf[0] = (uchar_t)0x00;
i2c_tp->i2c_wbuf[1] = rtc->rtc_sec;
i2c_tp->i2c_wbuf[2] = rtc->rtc_min;
i2c_tp->i2c_wbuf[3] = rtc->rtc_hrs;
i2c_tp->i2c_wbuf[4] = rtc->rtc_dow;
i2c_tp->i2c_wbuf[5] = rtc->rtc_dom;
i2c_tp->i2c_wbuf[6] = rtc->rtc_mon;
i2c_tp->i2c_wbuf[7] = rtc->rtc_year;
i2c_tp->i2c_wlen = 8;
if ((i2c_cmd_status = i2c_transfer(statep->ds1307_i2c_hdl,
i2c_tp)) != I2C_SUCCESS) {
(void) i2c_transfer_free(statep->ds1307_i2c_hdl, i2c_tp);
/* delay(drv_usectohz(I2C_DELAY)); */
drv_usecwait(I2C_DELAY);
return (i2c_cmd_status);
}
tod_read[0] = -1; /* invalidate saved data from read routine */
(void) i2c_transfer_free(statep->ds1307_i2c_hdl, i2c_tp);
return (i2c_cmd_status);
}
/*
* Drains any FIFOs in the card, then pauses it
*/
static void
pcn_suspend(pcn_t *pcnp)
{
uint32_t val;
int i;
PCN_CSR_SETBIT(pcnp, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
for (i = 0; i < 5000; i++) {
if ((val = pcn_csr_read(pcnp, PCN_CSR_EXTCTL1)) &
PCN_EXTCTL1_SPND)
return;
drv_usecwait(1000);
}
pcn_error(pcnp->pcn_dip, "Unable to suspend, EXTCTL1 was 0x%b", val,
PCN_EXTCTL1_STR);
}
/*
* audioixp_codec_ready()
*
* Description:
* This routine checks the state of codecs. It checks the flag to confirm
* that primary codec is ready.
*
* Arguments:
* audioixp_state_t *state The device's state structure
*
* Returns:
* DDI_SUCCESS codec is ready
* DDI_FAILURE codec is not ready
*/
static int
audioixp_codec_ready(audioixp_state_t *statep)
{
uint32_t sr;
PUT32(IXP_AUDIO_INT, 0xffffffff);
drv_usecwait(1000);
sr = GET32(IXP_AUDIO_INT);
if (sr & IXP_AUDIO_INT_CODEC0_NOT_READY) {
PUT32(IXP_AUDIO_INT, IXP_AUDIO_INT_CODEC0_NOT_READY);
audio_dev_warn(statep->adev, "primary codec not ready");
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* audioixp_codec_sync()
*
* Description:
* Serialize access to the AC97 audio mixer registers.
*
* Arguments:
* audioixp_state_t *state The device's state structure
*
* Returns:
* DDI_SUCCESS Ready for an I/O access to the codec
* DDI_FAILURE An I/O access is currently in progress, can't
* perform another I/O access.
*/
static int
audioixp_codec_sync(audioixp_state_t *statep)
{
int i;
uint32_t cmd;
for (i = 0; i < 300; i++) {
cmd = GET32(IXP_AUDIO_OUT_PHY_ADDR_DATA);
if (!(cmd & IXP_AUDIO_OUT_PHY_EN)) {
return (DDI_SUCCESS);
}
drv_usecwait(10);
}
audio_dev_warn(statep->adev, "unable to synchronize codec");
return (DDI_FAILURE);
}
void
efe_stop(efe_t *efep)
{
ASSERT(mutex_owned(&efep->efe_intrlock));
ASSERT(mutex_owned(&efep->efe_txlock));
efe_intr_disable(efep);
PUTCSR(efep, CSR_COMMAND, COMMAND_STOP_RX);
efe_stop_dma(efep);
PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
drv_usecwait(RESET_DELAY);
PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN);
}
boolean_t
arn_stoprecv(struct arn_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
boolean_t stopped;
ath9k_hw_stoppcurecv(ah);
ath9k_hw_setrxfilter(ah, 0);
stopped = ath9k_hw_stopdmarecv(ah);
/* 3ms is long enough for 1 frame ??? */
drv_usecwait(3000);
sc->sc_rxlink = NULL;
return (stopped);
}
