static void hns_gmac_port_mode_get(void *mac_drv, struct hns_gmac_port_mode_cfg *port_mode) { u32 tx_ctrl; u32 recv_ctrl; struct mac_driver *drv = (struct mac_driver *)mac_drv; port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S); tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG); port_mode->max_frm_size = dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S); port_mode->short_runts_thr = dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG, GMAC_SHORT_RUNTS_THR_M, GMAC_SHORT_RUNTS_THR_S); port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B); port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B); port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B); port_mode->runt_pkt_en = dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B); port_mode->strip_pad_en = dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B); }
void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb, const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE]) { int i; int reg_value; for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) { reg_value = dsaf_read_dev(ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4); dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M, PPEV2_CFG_RSS_TBL_4N0_S, rss_tab[i * 4 + 0] & 0x1F); dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M, PPEV2_CFG_RSS_TBL_4N1_S, rss_tab[i * 4 + 1] & 0x1F); dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M, PPEV2_CFG_RSS_TBL_4N2_S, rss_tab[i * 4 + 2] & 0x1F); dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M, PPEV2_CFG_RSS_TBL_4N3_S, rss_tab[i * 4 + 3] & 0x1F); dsaf_write_dev( ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value); } }
/** *hns_xgmac_pma_fec_enable - xgmac PMA FEC enable *@drv: mac driver *@tx_value: tx value *@rx_value: rx value *return status */ static void hns_xgmac_pma_fec_enable(struct mac_driver *drv, u32 tx_value, u32 rx_value) { u32 origin = dsaf_read_dev(drv, XGMAC_PMA_FEC_CONTROL_REG); dsaf_set_bit(origin, XGMAC_PMA_FEC_CTL_TX_B, !!tx_value); dsaf_set_bit(origin, XGMAC_PMA_FEC_CTL_RX_B, !!rx_value); dsaf_write_dev(drv, XGMAC_PMA_FEC_CONTROL_REG, origin); }
/** *hns_xgmac_pausefrm_cfg - set pause param about xgmac *@mac_drv: mac driver *@newval:enable of pad and crc */ static void hns_xgmac_pausefrm_cfg(void *mac_drv, u32 rx_en, u32 tx_en) { struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 origin = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); dsaf_set_bit(origin, XGMAC_PAUSE_CTL_TX_B, !!tx_en); dsaf_set_bit(origin, XGMAC_PAUSE_CTL_RX_B, !!rx_en); dsaf_write_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG, origin); }
/** *hns_gmac_get_en - get port enable *@mac_drv:mac device *@rx:rx enable *@tx:tx enable */ static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx) { struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 porten; porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG); *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B); *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B); }
/** *hns_xgmac_get_pausefrm_cfg - get xgmac pause param *@mac_drv: mac driver *@rx_en:xgmac rx pause enable *@tx_en:xgmac tx pause enable */ static void hns_xgmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_en, u32 *tx_en) { struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 pause_ctrl; pause_ctrl = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); *rx_en = dsaf_get_bit(pause_ctrl, XGMAC_PAUSE_CTL_RX_B); *tx_en = dsaf_get_bit(pause_ctrl, XGMAC_PAUSE_CTL_TX_B); }
static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval) { u32 tx_ctrl; struct mac_driver *drv = (struct mac_driver *)mac_drv; tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval); dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval); dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); }
/** *hns_xgmac_config_pad_and_crc - set xgmac pad and crc enable the same time *@mac_drv: mac driver *@newval:enable of pad and crc */ static void hns_xgmac_config_pad_and_crc(void *mac_drv, u8 newval) { struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 origin = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG); dsaf_set_bit(origin, XGMAC_CTL_TX_PAD_B, !!newval); dsaf_set_bit(origin, XGMAC_CTL_TX_FCS_B, !!newval); dsaf_set_bit(origin, XGMAC_CTL_RX_FCS_B, !!newval); dsaf_write_dev(drv, XGMAC_MAC_CONTROL_REG, origin); }
static void hns_gmac_tx_loop_pkt_dis(void *mac_drv) { u32 tx_loop_pkt_pri; struct mac_driver *drv = (struct mac_driver *)mac_drv; tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG); dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1); dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0); dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri); }
/** *hns_rcb_reset_ring_hw - ring reset *@q: ring struct pointer */ void hns_rcb_reset_ring_hw(struct hnae_queue *q) { u32 wait_cnt; u32 try_cnt = 0; u32 could_ret; u32 tx_fbd_num; while (try_cnt++ < RCB_RESET_TRY_TIMES) { usleep_range(100, 200); tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG); if (tx_fbd_num) continue; dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0); dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1); msleep(20); could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST); wait_cnt = 0; while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) { dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0); dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1); msleep(20); could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST); wait_cnt++; } dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0); if (could_ret) break; } if (try_cnt >= RCB_RESET_TRY_TIMES) dev_err(q->dev->dev, "port%d reset ring fail\n", hns_ae_get_vf_cb(q->handle)->port_index); }
/** * hns_ppe_set_qid - set ppe qid * @ppe_common: ppe common device * @qid: queue id */ static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid) { u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, PPE_CFG_QID_MODE_DEF_QID_S)) { dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, PPE_CFG_QID_MODE_DEF_QID_S, qid); dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod); } }
static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en, u32 *tx_pause_en) { u32 pause_en; struct mac_driver *drv = (struct mac_driver *)mac_drv; pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B); *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B); }
static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en, u32 tx_pause_en) { u32 pause_en; struct mac_driver *drv = (struct mac_driver *)mac_drv; pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en); dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en); dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en); }
/** *hns_rcb_wait_fbd_clean - clean fbd *@qs: ring struct pointer array *@qnum: num of array *@flag: tx or rx flag */ void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag) { int i, wait_cnt; u32 fbd_num; for (wait_cnt = i = 0; i < q_num; wait_cnt++) { usleep_range(200, 300); fbd_num = 0; if (flag & RCB_INT_FLAG_TX) fbd_num += dsaf_read_dev(qs[i], RCB_RING_TX_RING_FBDNUM_REG); if (flag & RCB_INT_FLAG_RX) fbd_num += dsaf_read_dev(qs[i], RCB_RING_RX_RING_FBDNUM_REG); if (!fbd_num) i++; if (wait_cnt >= 10000) break; } if (i < q_num) dev_err(qs[i]->handle->owner_dev, "queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num); }
/** *hns_xgmac_get_info - get xgmac information *@mac_drv: mac driver *@mac_info:mac information */ static void hns_xgmac_get_info(void *mac_drv, struct mac_info *mac_info) { struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 pause_time, pause_ctrl, port_mode, ctrl_val; ctrl_val = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG); mac_info->pad_and_crc_en = dsaf_get_bit(ctrl_val, XGMAC_CTL_TX_PAD_B); mac_info->auto_neg = 0; pause_time = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_TIME_REG); mac_info->tx_pause_time = pause_time; port_mode = dsaf_read_dev(drv, XGMAC_PORT_MODE_REG); mac_info->port_en = dsaf_get_field(port_mode, XGMAC_PORT_MODE_TX_M, XGMAC_PORT_MODE_TX_S) && dsaf_get_field(port_mode, XGMAC_PORT_MODE_RX_M, XGMAC_PORT_MODE_RX_S); mac_info->duplex = 1; mac_info->speed = MAC_SPEED_10000; pause_ctrl = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); mac_info->rx_pause_en = dsaf_get_bit(pause_ctrl, XGMAC_PAUSE_CTL_RX_B); mac_info->tx_pause_en = dsaf_get_bit(pause_ctrl, XGMAC_PAUSE_CTL_TX_B); }
static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr) { struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 high_val = mac_addr[1] | (mac_addr[0] << 8); u32 low_val = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) | (mac_addr[2] << 24); u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG); u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B); dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val); dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG, high_val | (sta_addr_en << GMAC_ADDR_EN_B)); }
static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed, u32 full_duplex) { u32 tx_ctrl; struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B, !!full_duplex); switch (speed) { case MAC_SPEED_10: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6); break; case MAC_SPEED_100: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7); break; case MAC_SPEED_1000: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8); break; default: dev_err(drv->dev, "hns_gmac_adjust_link fail, speed%d mac%d\n", speed, drv->mac_id); return -EINVAL; } tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1); dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1); dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG, GMAC_MODE_CHANGE_EB_B, 1); return 0; }
static int hns_gmac_wait_fifo_clean(void *mac_drv) { struct mac_driver *drv = (struct mac_driver *)mac_drv; int wait_cnt; u32 val; wait_cnt = 0; while (wait_cnt++ < HNS_MAX_WAIT_CNT) { val = dsaf_read_dev(drv, GMAC_FIFO_STATE_REG); /* bit5~bit0 is not send complete pkts */ if ((val & 0x3f) == 0) break; usleep_range(100, 200); } if (wait_cnt >= HNS_MAX_WAIT_CNT) { dev_err(drv->dev, "hns ge %d fifo was not idle.\n", drv->mac_id); return -EBUSY; } return 0; }
void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb) { struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; hw_stats->rx_pkts_from_sw += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); hw_stats->rx_pkts += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); hw_stats->rx_drop_no_bd += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); hw_stats->rx_alloc_buf_fail += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); hw_stats->rx_alloc_buf_wait += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); hw_stats->rx_drop_no_buf += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); hw_stats->rx_err_fifo_full += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); hw_stats->tx_bd_form_rcb += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); hw_stats->tx_pkts_from_rcb += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); hw_stats->tx_pkts += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); hw_stats->tx_err_fifo_empty += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); hw_stats->tx_err_checksum += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); }
/** *hns_xgmac_get_link_status - get xgmac link status *@mac_drv: mac driver *@link_stat: xgmac link stat */ static void hns_xgmac_get_link_status(void *mac_drv, u32 *link_stat) { struct mac_driver *drv = (struct mac_driver *)mac_drv; *link_stat = dsaf_read_dev(drv, XGMAC_LINK_STATUS_REG); }
void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data) { struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb; u32 *regs = data; u32 i; u32 offset; /* ppe common registers */ regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG); regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG); regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG); regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG); for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) { offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i; regs[5 + i] = dsaf_read_dev(ppe_common, offset); offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i; regs[5 + i + DSAF_TOTAL_QUEUE_NUM] = dsaf_read_dev(ppe_common, offset); offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i; regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2] = dsaf_read_dev(ppe_common, offset); offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i; regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3] = dsaf_read_dev(ppe_common, offset); } /* mark end of ppe regs */ for (i = 521; i < 524; i++) regs[i] = 0xeeeeeeee; /* ppe channel registers */ regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG); regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG); regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG); regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG); regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG); regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG); regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG); regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG); regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG); regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG); regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG); regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG); regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG); regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG); regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG); regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG); regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG); regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG); regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG); regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG); regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG); /* ppe static */ regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG); regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG); regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG); regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG); regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG); regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG); regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG); regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG); regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG); regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG); regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG); regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG); regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG); regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG); /* mark end of ppe regs */ for (i = 572; i < 576; i++) regs[i] = 0xeeeeeeee; }
static void hns_gmac_get_regs(void *mac_drv, void *data) { u32 *regs = data; int i; struct mac_driver *drv = (struct mac_driver *)mac_drv; /* base config registers */ regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG); regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG); regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG); regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG); regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG); regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG); regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG); regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG); regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG); regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG); regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG); regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG); regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG); regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG); regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG); /* rx static registers */ regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG); regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG); regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG); regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG); regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG); regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG); regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG); regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG); regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG); regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG); regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG); regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG); regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG); regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG); regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG); regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG); regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG); regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG); regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG); regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG); regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG); regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG); regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG); regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG); regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG); /* tx static registers */ regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG); regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG); regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG); regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG); regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG); regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG); regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG); regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG); regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG); regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG); regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG); regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG); regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG); regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG); regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG); regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG); regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG); regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME); regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG); regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG); regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG); regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG); regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG); regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG); regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG); regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG); regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG); regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG); regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG); regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG); regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG); regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG); regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG); regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG); regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG); regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG); regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG); regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG); regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG); regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG); regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG); regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG); regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG); regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG); regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG); regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG); regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG); /* mark end of mac regs */ for (i = 89; i < 96; i++) regs[i] = 0xaaaaaaaa; }
/** *hns_xgmac_get_regs - dump xgmac regs *@mac_drv: mac driver *@cmd:ethtool cmd *@data:data for value of regs */ static void hns_xgmac_get_regs(void *mac_drv, void *data) { u32 i = 0; struct mac_driver *drv = (struct mac_driver *)mac_drv; u32 *regs = data; u64 qtmp; /* base config registers */ regs[0] = dsaf_read_dev(drv, XGMAC_INT_STATUS_REG); regs[1] = dsaf_read_dev(drv, XGMAC_INT_ENABLE_REG); regs[2] = dsaf_read_dev(drv, XGMAC_INT_SET_REG); regs[3] = dsaf_read_dev(drv, XGMAC_IERR_U_INFO_REG); regs[4] = dsaf_read_dev(drv, XGMAC_OVF_INFO_REG); regs[5] = dsaf_read_dev(drv, XGMAC_OVF_CNT_REG); regs[6] = dsaf_read_dev(drv, XGMAC_PORT_MODE_REG); regs[7] = dsaf_read_dev(drv, XGMAC_CLK_ENABLE_REG); regs[8] = dsaf_read_dev(drv, XGMAC_RESET_REG); regs[9] = dsaf_read_dev(drv, XGMAC_LINK_CONTROL_REG); regs[10] = dsaf_read_dev(drv, XGMAC_LINK_STATUS_REG); regs[11] = dsaf_read_dev(drv, XGMAC_SPARE_REG); regs[12] = dsaf_read_dev(drv, XGMAC_SPARE_CNT_REG); regs[13] = dsaf_read_dev(drv, XGMAC_MAC_ENABLE_REG); regs[14] = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG); regs[15] = dsaf_read_dev(drv, XGMAC_MAC_IPG_REG); regs[16] = dsaf_read_dev(drv, XGMAC_MAC_MSG_CRC_EN_REG); regs[17] = dsaf_read_dev(drv, XGMAC_MAC_MSG_IMG_REG); regs[18] = dsaf_read_dev(drv, XGMAC_MAC_MSG_FC_CFG_REG); regs[19] = dsaf_read_dev(drv, XGMAC_MAC_MSG_TC_CFG_REG); regs[20] = dsaf_read_dev(drv, XGMAC_MAC_PAD_SIZE_REG); regs[21] = dsaf_read_dev(drv, XGMAC_MAC_MIN_PKT_SIZE_REG); regs[22] = dsaf_read_dev(drv, XGMAC_MAC_MAX_PKT_SIZE_REG); regs[23] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG); regs[24] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_TIME_REG); regs[25] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_GAP_REG); regs[26] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG); regs[27] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG); regs[28] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_PEER_MAC_H_REG); regs[29] = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_PEER_MAC_L_REG); regs[30] = dsaf_read_dev(drv, XGMAC_MAC_PFC_PRI_EN_REG); regs[31] = dsaf_read_dev(drv, XGMAC_MAC_1588_CTRL_REG); regs[32] = dsaf_read_dev(drv, XGMAC_MAC_1588_TX_PORT_DLY_REG); regs[33] = dsaf_read_dev(drv, XGMAC_MAC_1588_RX_PORT_DLY_REG); regs[34] = dsaf_read_dev(drv, XGMAC_MAC_1588_ASYM_DLY_REG); regs[35] = dsaf_read_dev(drv, XGMAC_MAC_1588_ADJUST_CFG_REG); regs[36] = dsaf_read_dev(drv, XGMAC_MAC_Y1731_ETH_TYPE_REG); regs[37] = dsaf_read_dev(drv, XGMAC_MAC_MIB_CONTROL_REG); regs[38] = dsaf_read_dev(drv, XGMAC_MAC_WAN_RATE_ADJUST_REG); regs[39] = dsaf_read_dev(drv, XGMAC_MAC_TX_ERR_MARK_REG); regs[40] = dsaf_read_dev(drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG); regs[41] = dsaf_read_dev(drv, XGMAC_MAC_RX_LF_RF_STATUS_REG); regs[42] = dsaf_read_dev(drv, XGMAC_MAC_TX_RUNT_PKT_CNT_REG); regs[43] = dsaf_read_dev(drv, XGMAC_MAC_RX_RUNT_PKT_CNT_REG); regs[44] = dsaf_read_dev(drv, XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG); regs[45] = dsaf_read_dev(drv, XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG); regs[46] = dsaf_read_dev(drv, XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG); regs[47] = dsaf_read_dev(drv, XGMAC_MAC_RX_ERR_MSG_CNT_REG); regs[48] = dsaf_read_dev(drv, XGMAC_MAC_RX_ERR_EFD_CNT_REG); regs[49] = dsaf_read_dev(drv, XGMAC_MAC_ERR_INFO_REG); regs[50] = dsaf_read_dev(drv, XGMAC_MAC_DBG_INFO_REG); regs[51] = dsaf_read_dev(drv, XGMAC_PCS_BASER_SYNC_THD_REG); regs[52] = dsaf_read_dev(drv, XGMAC_PCS_STATUS1_REG); regs[53] = dsaf_read_dev(drv, XGMAC_PCS_BASER_STATUS1_REG); regs[54] = dsaf_read_dev(drv, XGMAC_PCS_BASER_STATUS2_REG); regs[55] = dsaf_read_dev(drv, XGMAC_PCS_BASER_SEEDA_0_REG); regs[56] = dsaf_read_dev(drv, XGMAC_PCS_BASER_SEEDA_1_REG); regs[57] = dsaf_read_dev(drv, XGMAC_PCS_BASER_SEEDB_0_REG); regs[58] = dsaf_read_dev(drv, XGMAC_PCS_BASER_SEEDB_1_REG); regs[59] = dsaf_read_dev(drv, XGMAC_PCS_BASER_TEST_CONTROL_REG); regs[60] = dsaf_read_dev(drv, XGMAC_PCS_BASER_TEST_ERR_CNT_REG); regs[61] = dsaf_read_dev(drv, XGMAC_PCS_DBG_INFO_REG); regs[62] = dsaf_read_dev(drv, XGMAC_PCS_DBG_INFO1_REG); regs[63] = dsaf_read_dev(drv, XGMAC_PCS_DBG_INFO2_REG); regs[64] = dsaf_read_dev(drv, XGMAC_PCS_DBG_INFO3_REG); regs[65] = dsaf_read_dev(drv, XGMAC_PMA_ENABLE_REG); regs[66] = dsaf_read_dev(drv, XGMAC_PMA_CONTROL_REG); regs[67] = dsaf_read_dev(drv, XGMAC_PMA_SIGNAL_STATUS_REG); regs[68] = dsaf_read_dev(drv, XGMAC_PMA_DBG_INFO_REG); regs[69] = dsaf_read_dev(drv, XGMAC_PMA_FEC_ABILITY_REG); regs[70] = dsaf_read_dev(drv, XGMAC_PMA_FEC_CONTROL_REG); regs[71] = dsaf_read_dev(drv, XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG); regs[72] = dsaf_read_dev(drv, XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG); /* status registers */ #define hns_xgmac_cpy_q(p, q) \ do {\ *(p) = (u32)(q);\ *((p) + 1) = (u32)((q) >> 32);\ } while (0) qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_FRAGMENT); hns_xgmac_cpy_q(®s[73], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_UNDERSIZE); hns_xgmac_cpy_q(®s[75], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_UNDERMIN); hns_xgmac_cpy_q(®s[77], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_64OCTETS); hns_xgmac_cpy_q(®s[79], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_65TO127OCTETS); hns_xgmac_cpy_q(®s[81], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_128TO255OCTETS); hns_xgmac_cpy_q(®s[83], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_256TO511OCTETS); hns_xgmac_cpy_q(®s[85], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_512TO1023OCTETS); hns_xgmac_cpy_q(®s[87], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_1024TO1518OCTETS); hns_xgmac_cpy_q(®s[89], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_1519TOMAXOCTETS); hns_xgmac_cpy_q(®s[91], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_1519TOMAXOCTETSOK); hns_xgmac_cpy_q(®s[93], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_OVERSIZE); hns_xgmac_cpy_q(®s[95], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PKTS_JABBER); hns_xgmac_cpy_q(®s[97], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_GOODPKTS); hns_xgmac_cpy_q(®s[99], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_GOODOCTETS); hns_xgmac_cpy_q(®s[101], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_TOTAL_PKTS); hns_xgmac_cpy_q(®s[103], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_TOTALOCTETS); hns_xgmac_cpy_q(®s[105], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_UNICASTPKTS); hns_xgmac_cpy_q(®s[107], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_MULTICASTPKTS); hns_xgmac_cpy_q(®s[109], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_BROADCASTPKTS); hns_xgmac_cpy_q(®s[111], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI0PAUSEPKTS); hns_xgmac_cpy_q(®s[113], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI1PAUSEPKTS); hns_xgmac_cpy_q(®s[115], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI2PAUSEPKTS); hns_xgmac_cpy_q(®s[117], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI3PAUSEPKTS); hns_xgmac_cpy_q(®s[119], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI4PAUSEPKTS); hns_xgmac_cpy_q(®s[121], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI5PAUSEPKTS); hns_xgmac_cpy_q(®s[123], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI6PAUSEPKTS); hns_xgmac_cpy_q(®s[125], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_PRI7PAUSEPKTS); hns_xgmac_cpy_q(®s[127], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_MACCTRLPKTS); hns_xgmac_cpy_q(®s[129], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_1731PKTS); hns_xgmac_cpy_q(®s[131], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_1588PKTS); hns_xgmac_cpy_q(®s[133], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_FROMAPPGOODPKTS); hns_xgmac_cpy_q(®s[135], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_FROMAPPBADPKTS); hns_xgmac_cpy_q(®s[137], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_ERRALLPKTS); hns_xgmac_cpy_q(®s[139], qtmp); /* RX */ qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_FRAGMENT); hns_xgmac_cpy_q(®s[141], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTSUNDERSIZE); hns_xgmac_cpy_q(®s[143], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_UNDERMIN); hns_xgmac_cpy_q(®s[145], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_64OCTETS); hns_xgmac_cpy_q(®s[147], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_65TO127OCTETS); hns_xgmac_cpy_q(®s[149], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_128TO255OCTETS); hns_xgmac_cpy_q(®s[151], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_256TO511OCTETS); hns_xgmac_cpy_q(®s[153], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_512TO1023OCTETS); hns_xgmac_cpy_q(®s[155], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_1024TO1518OCTETS); hns_xgmac_cpy_q(®s[157], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_1519TOMAXOCTETS); hns_xgmac_cpy_q(®s[159], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_1519TOMAXOCTETSOK); hns_xgmac_cpy_q(®s[161], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_OVERSIZE); hns_xgmac_cpy_q(®s[163], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PKTS_JABBER); hns_xgmac_cpy_q(®s[165], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_GOODPKTS); hns_xgmac_cpy_q(®s[167], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_GOODOCTETS); hns_xgmac_cpy_q(®s[169], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_TOTAL_PKTS); hns_xgmac_cpy_q(®s[171], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_TOTALOCTETS); hns_xgmac_cpy_q(®s[173], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_UNICASTPKTS); hns_xgmac_cpy_q(®s[175], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_MULTICASTPKTS); hns_xgmac_cpy_q(®s[177], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_BROADCASTPKTS); hns_xgmac_cpy_q(®s[179], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI0PAUSEPKTS); hns_xgmac_cpy_q(®s[181], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI1PAUSEPKTS); hns_xgmac_cpy_q(®s[183], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI2PAUSEPKTS); hns_xgmac_cpy_q(®s[185], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI3PAUSEPKTS); hns_xgmac_cpy_q(®s[187], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI4PAUSEPKTS); hns_xgmac_cpy_q(®s[189], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI5PAUSEPKTS); hns_xgmac_cpy_q(®s[191], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI6PAUSEPKTS); hns_xgmac_cpy_q(®s[193], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_PRI7PAUSEPKTS); hns_xgmac_cpy_q(®s[195], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_MACCTRLPKTS); hns_xgmac_cpy_q(®s[197], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_SENDAPPGOODPKTS); hns_xgmac_cpy_q(®s[199], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_TX_SENDAPPBADPKTS); hns_xgmac_cpy_q(®s[201], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_1731PKTS); hns_xgmac_cpy_q(®s[203], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_SYMBOLERRPKTS); hns_xgmac_cpy_q(®s[205], qtmp); qtmp = hns_mac_reg_read64(drv, XGMAC_RX_FCSERRPKTS); hns_xgmac_cpy_q(®s[207], qtmp); /* mark end of mac regs */ for (i = 208; i < 214; i++) regs[i] = 0xaaaaaaaa; }
void hns_gmac_update_stats(void *mac_drv) { struct mac_hw_stats *hw_stats = NULL; struct mac_driver *drv = (struct mac_driver *)mac_drv; hw_stats = &drv->mac_cb->hw_stats; /* RX */ hw_stats->rx_good_bytes += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG); hw_stats->rx_bad_bytes += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG); hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG); hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG); hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG); hw_stats->rx_64bytes += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG); hw_stats->rx_65to127 += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG); hw_stats->rx_128to255 += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG); hw_stats->rx_256to511 += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG); hw_stats->rx_512to1023 += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG); hw_stats->rx_1024to1518 += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG); hw_stats->rx_1519tomax += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG); hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG); hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG); hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG); hw_stats->rx_align_err += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG); hw_stats->rx_oversize += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG); hw_stats->rx_jabber_err += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG); hw_stats->rx_pfc_tc0 += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG); hw_stats->rx_unknown_ctrl += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG); hw_stats->rx_long_err += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG); hw_stats->rx_minto64 += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG); hw_stats->rx_under_min += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG); hw_stats->rx_filter_pkts += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG); hw_stats->rx_filter_bytes += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG); hw_stats->rx_fifo_overrun_err += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG); hw_stats->rx_len_err += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG); hw_stats->rx_comma_err += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG); /* TX */ hw_stats->tx_good_bytes += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG); hw_stats->tx_bad_bytes += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG); hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG); hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG); hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG); hw_stats->tx_64bytes += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG); hw_stats->tx_65to127 += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG); hw_stats->tx_128to255 += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG); hw_stats->tx_256to511 += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG); hw_stats->tx_512to1023 += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG); hw_stats->tx_1024to1518 += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG); hw_stats->tx_1519tomax += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG); hw_stats->tx_jabber_err += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG); hw_stats->tx_underrun_err += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG); hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG); hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG); hw_stats->tx_pfc_tc0 += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG); }