/**
* hns_xgmac__lf_rf_control_init - initial the lf rf control register
* @mac_drv: mac driver
*/
static void hns_xgmac_lf_rf_control_init(struct mac_driver *mac_drv)
{
u32 val = 0;
dsaf_set_bit(val, XGMAC_UNIDIR_EN_B, 0);
dsaf_set_bit(val, XGMAC_RF_TX_EN_B, 1);
dsaf_set_field(val, XGMAC_LF_RF_INSERT_M, XGMAC_LF_RF_INSERT_S, 0);
dsaf_write_reg(mac_drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG, val);
}
/**
*hns_xgmac_pausefrm_cfg - set pause param about xgmac
*@mac_drv: mac driver
*@newval:enable of pad and crc
*/
static void hns_xgmac_pausefrm_cfg(void *mac_drv, u32 rx_en, u32 tx_en)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
u32 origin = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG);
dsaf_set_bit(origin, XGMAC_PAUSE_CTL_TX_B, !!tx_en);
dsaf_set_bit(origin, XGMAC_PAUSE_CTL_RX_B, !!rx_en);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG, origin);
}
/**
*hns_xgmac_pma_fec_enable - xgmac PMA FEC enable
*@drv: mac driver
*@tx_value: tx value
*@rx_value: rx value
*return status
*/
static void hns_xgmac_pma_fec_enable(struct mac_driver *drv, u32 tx_value,
u32 rx_value)
{
u32 origin = dsaf_read_dev(drv, XGMAC_PMA_FEC_CONTROL_REG);
dsaf_set_bit(origin, XGMAC_PMA_FEC_CTL_TX_B, !!tx_value);
dsaf_set_bit(origin, XGMAC_PMA_FEC_CTL_RX_B, !!rx_value);
dsaf_write_dev(drv, XGMAC_PMA_FEC_CONTROL_REG, origin);
}
/**
*hns_xgmac_config_pad_and_crc - set xgmac pad and crc enable the same time
*@mac_drv: mac driver
*@newval:enable of pad and crc
*/
static void hns_xgmac_config_pad_and_crc(void *mac_drv, u8 newval)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
u32 origin = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG);
dsaf_set_bit(origin, XGMAC_CTL_TX_PAD_B, !!newval);
dsaf_set_bit(origin, XGMAC_CTL_TX_FCS_B, !!newval);
dsaf_set_bit(origin, XGMAC_CTL_RX_FCS_B, !!newval);
dsaf_write_dev(drv, XGMAC_MAC_CONTROL_REG, origin);
}
static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
{
u32 tx_loop_pkt_pri;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
}
static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
{
u32 tx_ctrl;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
}
static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
u32 tx_pause_en)
{
u32 pause_en;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
}
/*clr ppe exception irq*/
static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
{
u32 clr_vlue = 0xfffffffful;
u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
u32 vld_msk = 0;
/*only care bit 0,1,7*/
dsaf_set_bit(vld_msk, 0, 1);
dsaf_set_bit(vld_msk, 1, 1);
dsaf_set_bit(vld_msk, 7, 1);
/*clr sts**/
dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
/*for some reserved bits, so set 0**/
dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
}
static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
u32 full_duplex)
{
u32 tx_ctrl;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
GMAC_DUPLEX_TYPE_B, !!full_duplex);
switch (speed) {
case MAC_SPEED_10:
dsaf_set_dev_field(
drv, GMAC_PORT_MODE_REG,
GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
break;
case MAC_SPEED_100:
dsaf_set_dev_field(
drv, GMAC_PORT_MODE_REG,
GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
break;
case MAC_SPEED_1000:
dsaf_set_dev_field(
drv, GMAC_PORT_MODE_REG,
GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
break;
default:
dev_err(drv->dev,
"hns_gmac_adjust_link fail, speed%d mac%d\n",
speed, drv->mac_id);
return -EINVAL;
}
tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1);
dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1);
dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
GMAC_MODE_CHANGE_EB_B, 1);
return 0;
}
int cpld_set_led_id(struct hns_mac_cb *mac_cb,
enum hnae_led_state status)
{
switch (status) {
case HNAE_LED_ACTIVE:
mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
CPLD_LED_ON_VALUE);
dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
return 2;
case HNAE_LED_INACTIVE:
dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
CPLD_LED_DEFAULT_VALUE);
dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
break;
default:
break;
}
return 0;
}
void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
u16 speed, int data)
{
int speed_reg = 0;
u8 value;
if (!mac_cb) {
pr_err("sfp_led_opt mac_dev is null!\n");
return;
}
if (!mac_cb->cpld_vaddr) {
dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
mac_cb->mac_id);
return;
}
if (speed == MAC_SPEED_10000)
speed_reg = 1;
value = mac_cb->cpld_led_value;
if (link_status) {
dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
dsaf_set_field(value, DSAF_LED_SPEED_M,
DSAF_LED_SPEED_S, speed_reg);
dsaf_set_bit(value, DSAF_LED_DATA_B, data);
if (value != mac_cb->cpld_led_value) {
dsaf_write_b(mac_cb->cpld_vaddr, value);
mac_cb->cpld_led_value = value;
}
} else {
dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}
}
