int dpi_check_timings(struct omap_dss_device *dssdev, struct omap_video_timings *timings) { struct dispc_clock_info dispc_cinfo; bool is_tft; if (!dispc_lcd_timings_ok(timings)) return -EINVAL; if (timings->pixel_clock == 0) return -EINVAL; is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL { struct dsi_clock_info dsi_cinfo; int r = 0; if (cpu_is_omap44xx()) { dsi_cinfo.regn = 17; dsi_cinfo.regm = 150; dsi_cinfo.regm_dispc = 4; dsi_cinfo.regm_dsi = 4; dsi_cinfo.use_dss2_fck = true; r = dsi_calc_clock_rates(&dsi_cinfo); if (r) return r; dispc_find_clk_divs(is_tft, timings->pixel_clock * 1000, dsi_cinfo.dsi_pll_dispc_fclk, &dispc_cinfo); } else { r = dsi_pll_calc_clock_div_pck(dssdev->channel == OMAP_DSS_CHANNEL_LCD ? DSI1 : DSI2, is_tft, timings->pixel_clock * 1000, &dsi_cinfo, &dispc_cinfo); if (r) return r; } } #else /* #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL */ if (cpu_is_omap44xx()) dispc_find_clk_divs(is_tft, timings->pixel_clock * 1000, dss_clk_get_rate(DSS_CLK_FCK1), &dispc_cinfo); else { struct dss_clock_info dss_cinfo; int r = 0; r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo); if (r) return r; } #endif /* CONFIG_OMAP2_DSS_USE_DSI_PLL */ timings->pixel_clock = dispc_cinfo.pck / 1000; return 0; }
static int dpi_set_dsi_clk(enum omap_channel channel, bool is_tft, unsigned long pck_req, unsigned long *pck) { struct dsi_clock_info dsi_cinfo; struct dispc_clock_info dispc_cinfo; int r; enum omap_dsi_index ix; DSSDBG("DPI clk source is DSI PLL\n"); ix = (channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2; if (!cpu_is_omap44xx()) { r = dsi_pll_calc_clock_div_pck(ix, is_tft, pck_req, &dsi_cinfo, &dispc_cinfo); if (r) return r; } else { dsi_cinfo.regn = 16; dsi_cinfo.regm = 115; dsi_cinfo.regm_dispc = 3; dsi_cinfo.regm_dsi = 3; dsi_cinfo.use_dss2_fck = true; r = dsi_calc_clock_rates(channel, &dsi_cinfo); DSSDBG("dpi_set_dsi_clk: dsi_calc_clock_rates=%d\n", r); if (r) return r; dispc_find_clk_divs(is_tft, pck_req, dsi_cinfo.dsi_pll_dispc_fclk, &dispc_cinfo); } r = dsi_pll_set_clock_div(ix, &dsi_cinfo); DSSDBG("dpi_set_dsi_clk: dsi_pll_set_clock_div=%d\n", r); if (r) return r; if (cpu_is_omap44xx()){ dss_select_dispc_clk_source(ix, (ix == DSI1) ? DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1); dss_select_lcd_clk_source(ix, (ix == DSI1) ? DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1); }else{ dss_select_dispc_clk_source(ix, DSS_SRC_DSI1_PLL_FCLK); } dispc_set_clock_div(channel, &dispc_cinfo); *pck = dispc_cinfo.pck; return 0; }
static int dpi_set_dsi_clk(int lcd_channel_ix, bool is_tft, unsigned long pck_req, unsigned long *fck, int *lck_div, int *pck_div) { struct dsi_clock_info dsi_cinfo; struct dispc_clock_info dispc_cinfo; int r; printk(KERN_INFO "DPI set dsi clk"); if (!cpu_is_omap44xx()) { r = dsi_pll_calc_clock_div_pck(lcd_channel_ix, is_tft, pck_req, &dsi_cinfo, &dispc_cinfo); if (r) return r; } else { dispc_cinfo.lck_div = 1; dispc_cinfo.pck_div = 4; dsi_cinfo.regn = 19; dsi_cinfo.regm = 150; dsi_cinfo.regm3 = 4; dsi_cinfo.regm4 = 4; dsi_cinfo.use_dss2_fck = true; dsi_cinfo.highfreq = 0; dsi_calc_clock_rates(&dsi_cinfo); } r = dsi_pll_set_clock_div(lcd_channel_ix, &dsi_cinfo); if (r) return r; if (cpu_is_omap44xx()) dss_select_clk_source_dsi(lcd_channel_ix, 1, 1); else dss_select_clk_source(0, 1); r = dispc_set_clock_div(lcd_channel_ix, &dispc_cinfo); if (r) return r; *fck = dsi_cinfo.dsi1_pll_fclk; *lck_div = dispc_cinfo.lck_div; *pck_div = dispc_cinfo.pck_div; return 0; }