static int mapphone_panel_enable_te(struct omap_dss_device *dssdev, bool enable)
{
u8 data[3];
int ret;
if (enable == true) {
data[0] = EDISCO_CMD_SET_TEAR_ON;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_TEAR_SCANLINE;
data[1] = 0x03;
data[2] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
if (ret)
goto error;
} else {
data[0] = EDISCO_CMD_SET_TEAR_OFF;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
}
DBG(" edisco_ctrl_enable_te(%d) \n", enable);
return 0;
error:
return -EINVAL;
}
static void mapphone_panel_setup_update(struct omap_dss_device *dssdev,
u16 x, u16 y, u16 w, u16 h)
{
u8 data[5];
int ret;
struct mapphone_data *map_data = (struct mapphone_data *) dssdev->data;
if ((dssdev->panel.panel_id == MOT_DISP_MIPI_480_854_CM) ||
(dssdev->panel.panel_id == MOT_DISP_430_MIPI_480_854_CM)) {
if (atomic_cmpxchg(&map_data->state, PANEL_ENABLED,
PANEL_UPDATED) == PANEL_ENABLED) {
DBG("panel updated\n");
wake_up(&map_data->wait);
}
}
/* set page, column address */
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = y >> 8;
data[2] = y & 0xff;
data[3] = (y + h - 1) >> 8;
data[4] = (y + h - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
return;
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = x >> 8;
data[2] = x & 0xff;
data[3] = (x + w - 1) >> 8;
data[4] = (x + w - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
return;
}
static void sholes_panel_setup_update(struct omap_dss_device *dssdev,
u16 x, u16 y, u16 w, u16 h)
{
u8 data[5];
int ret;
/* set page, column address */
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = y >> 8;
data[2] = y & 0xff;
data[3] = (y + h - 1) >> 8;
data[4] = (y + h - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
return;
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = x >> 8;
data[2] = x & 0xff;
data[3] = (x + w - 1) >> 8;
data[4] = (x + w - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
return;
}
static int dsi_mipi_248_vm_320_240_panel_enable(struct omap_dss_device *dssdev)
{
u8 data[7];
int ret;
DBG(" dsi_mipi_248_vm_320_240_panel_enable() \n");
/* turn it on */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret)
goto error;
mdelay(10);
data[0] = EDISCO_CMD_SET_DISPLAY_ON;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret) {
printk(KERN_ERR "failed to send EDISCO_CMD_SET_DISPLAY_ON \n");
goto error;
}
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
static int hv070wx1_write_reg(struct omap_dss_device *dssdev, u8 reg, u8 val)
{
u8 buf[2];
buf[0] = reg;
buf[1] = val;
return dsi_vc_dcs_write(dssdev, 1, buf, 2);
}
static int dsi_mipi_cm_panel_on(struct omap_dss_device *dssdev)
{
u8 data = EDISCO_CMD_SET_DISPLAY_ON;
check_delay_timer(dssdev);
return dsi_vc_dcs_write(EDISCO_CMD_VC, &data, 1);
}
static int sholes_panel_display_on(struct omap_dss_device *dssdev)
{
u8 data = EDISCO_CMD_SET_DISPLAY_ON;
if (atomic_cmpxchg(&state, PANEL_OFF, PANEL_ON) ==
PANEL_OFF) {
return dsi_vc_dcs_write(EDISCO_CMD_VC, &data, 1);
}
return 0;
}
static void sholes_panel_disable(struct omap_dss_device *dssdev)
{
u8 data[1];
DBG("sholes_panel_ctrl_disable\n");
data[0] = EDISCO_CMD_SET_DISPLAY_OFF;
dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
data[0] = EDISCO_CMD_ENTER_SLEEP_MODE;
dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
msleep(120);
atomic_set(&state, PANEL_OFF);
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);
}
static int dsi_mipi_vm_panel_on(struct omap_dss_device *dssdev)
{
u8 data = EDISCO_CMD_SET_DISPLAY_ON;
int ret;
dsi_disable_vid_vc_enable_cmd_vc();
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, &data, 1);
dsi_disable_cmd_vc_enable_vid_vc();
return ret;
}
static void kd080d14_enable(struct intel_dsi_device *dsi)
{
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
DRM_DEBUG_KMS("\n");
printk("--->%s\n",__func__);
dsi_vc_dcs_write_0(intel_dsi, 0, 0x11);
msleep(300); //wait for 30ms
dsi_vc_dcs_write(intel_dsi, 0, cpt_enable_ic_power, sizeof(cpt_enable_ic_power));
msleep(150); //wait for 150ms
dsi_vc_dcs_write_0(intel_dsi, 0, 0x29);
msleep(50);
}
static int sholes_panel_enable_te(struct omap_dss_device *dssdev, bool enable)
{
u8 data[3];
int ret;
data[0] = EDISCO_CMD_SET_TEAR_ON;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_TEAR_SCANLINE;
data[1] = 0x03;
data[2] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
if (ret)
goto error;
DBG("edisco_ctrl_enable_te \n");
return 0;
error:
return -EINVAL;
}
void p088pw_send_otp_cmds(struct intel_dsi_device *dsi)
{
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
int sequence_line, i;
DRM_DEBUG_KMS(" p088pw_send_otp_cmds \n");
#if 1
sequence_line = sizeof(init_sequence) / sizeof(init_sequence[0]);
for(i = 0; i < sequence_line; i++)
{
dsi_vc_dcs_write(intel_dsi, 0, &init_sequence[i].para_list[0], init_sequence[i].count);
if(init_sequence[i].para_list[0] == 0x11)
msleep(120);
if(init_sequence[i].para_list[0] == 0x29)
msleep(20);
}
#endif
}
static void mapphone_panel_display_on(struct work_struct *work)
{
struct mapphone_data *map_data = container_of(work,
struct mapphone_data, work);
u8 data[7];
int state;
wait_event(map_data->wait, is_updated_or_off(map_data, &state));
if (state == PANEL_OFF) {
DBG("cancel panel on\n");
return;
}
DBG("panel_display_on\n");
map_data->dssdev->sync(map_data->dssdev);
data[0] = EDISCO_CMD_SET_DISPLAY_ON;
dsi_bus_lock();
dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
dsi_bus_unlock();
}
void kd080d14_send_otp_cmds(struct intel_dsi_device *dsi)
{
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
printk("--->%s\n",__func__);
dsi_vc_dcs_write(intel_dsi, 0, init_sequence1, sizeof(init_sequence1));
mdelay(10);
dsi_vc_dcs_write(intel_dsi, 0, init_sequence2, sizeof(init_sequence2));
mdelay(10);
dsi_vc_dcs_write(intel_dsi, 0, init_sequence3, sizeof(init_sequence3));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence4, sizeof(init_sequence4));
mdelay(10);
dsi_vc_dcs_write(intel_dsi, 0, init_sequence5, sizeof(init_sequence5));
mdelay(10);
dsi_vc_dcs_write(intel_dsi, 0, init_sequence6, sizeof(init_sequence6));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence7, sizeof(init_sequence7));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence8, sizeof(init_sequence8));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence9, sizeof(init_sequence9));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence10, sizeof(init_sequence10));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence11, sizeof(init_sequence11));
dsi_vc_dcs_write(intel_dsi, 0, init_sequence12, sizeof(init_sequence12));
}
void n080ice_gb1_send_otp_cmds(struct intel_dsi_device *dsi)
{
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
DRM_DEBUG_KMS("\n");
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_1, sizeof(innolux_init_sequence_1));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_2, sizeof(innolux_init_sequence_2));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_3, sizeof(innolux_init_sequence_3));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_4, sizeof(innolux_init_sequence_4));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_5, sizeof(innolux_init_sequence_5));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_6, sizeof(innolux_init_sequence_6));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_7, sizeof(innolux_init_sequence_7));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_8, sizeof(innolux_init_sequence_8));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_9, sizeof(innolux_init_sequence_9));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_10, sizeof(innolux_init_sequence_10));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_11, sizeof(innolux_init_sequence_11));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_12, sizeof(innolux_init_sequence_12));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_13, sizeof(innolux_init_sequence_13));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_14, sizeof(innolux_init_sequence_14));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_15, sizeof(innolux_init_sequence_15));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_16, sizeof(innolux_init_sequence_16));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_17, sizeof(innolux_init_sequence_17));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_18, sizeof(innolux_init_sequence_18));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_19, sizeof(innolux_init_sequence_19));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_20, sizeof(innolux_init_sequence_20));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_21, sizeof(innolux_init_sequence_21));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_22, sizeof(innolux_init_sequence_22));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_23, sizeof(innolux_init_sequence_23));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_24, sizeof(innolux_init_sequence_24));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_25, sizeof(innolux_init_sequence_25));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_26, sizeof(innolux_init_sequence_26));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_27, sizeof(innolux_init_sequence_27));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_28, sizeof(innolux_init_sequence_28));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_29, sizeof(innolux_init_sequence_29));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_30, sizeof(innolux_init_sequence_30));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_31, sizeof(innolux_init_sequence_31));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_32, sizeof(innolux_init_sequence_32));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_33, sizeof(innolux_init_sequence_33));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_34, sizeof(innolux_init_sequence_34));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_35, sizeof(innolux_init_sequence_35));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_36, sizeof(innolux_init_sequence_36));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_37, sizeof(innolux_init_sequence_37));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_38, sizeof(innolux_init_sequence_38));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_39, sizeof(innolux_init_sequence_39));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_40, sizeof(innolux_init_sequence_40));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_41, sizeof(innolux_init_sequence_41));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_42, sizeof(innolux_init_sequence_42));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_43, sizeof(innolux_init_sequence_43));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_44, sizeof(innolux_init_sequence_44));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_45, sizeof(innolux_init_sequence_45));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_46, sizeof(innolux_init_sequence_46));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_47, sizeof(innolux_init_sequence_47));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_48, sizeof(innolux_init_sequence_48));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_49, sizeof(innolux_init_sequence_49));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_50, sizeof(innolux_init_sequence_50));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_51, sizeof(innolux_init_sequence_51));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_52, sizeof(innolux_init_sequence_52));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_53, sizeof(innolux_init_sequence_53));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_54, sizeof(innolux_init_sequence_54));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_55, sizeof(innolux_init_sequence_55));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_56, sizeof(innolux_init_sequence_56));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_57, sizeof(innolux_init_sequence_57));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_58, sizeof(innolux_init_sequence_58));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_59, sizeof(innolux_init_sequence_59));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_60, sizeof(innolux_init_sequence_60));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_61, sizeof(innolux_init_sequence_61));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_62, sizeof(innolux_init_sequence_62));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_63, sizeof(innolux_init_sequence_63));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_64, sizeof(innolux_init_sequence_64));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_65, sizeof(innolux_init_sequence_65));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_66, sizeof(innolux_init_sequence_66));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_67, sizeof(innolux_init_sequence_67));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_68, sizeof(innolux_init_sequence_68));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_69, sizeof(innolux_init_sequence_69));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_70, sizeof(innolux_init_sequence_70));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_71, sizeof(innolux_init_sequence_71));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_72, sizeof(innolux_init_sequence_72));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_73, sizeof(innolux_init_sequence_73));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_74, sizeof(innolux_init_sequence_74));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_75, sizeof(innolux_init_sequence_75));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_76, sizeof(innolux_init_sequence_76));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_77, sizeof(innolux_init_sequence_77));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_78, sizeof(innolux_init_sequence_78));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_79, sizeof(innolux_init_sequence_79));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_80, sizeof(innolux_init_sequence_80));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_81, sizeof(innolux_init_sequence_81));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_82, sizeof(innolux_init_sequence_82));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_83, sizeof(innolux_init_sequence_83));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_84, sizeof(innolux_init_sequence_84));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_85, sizeof(innolux_init_sequence_85));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_86, sizeof(innolux_init_sequence_86));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_87, sizeof(innolux_init_sequence_87));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_88, sizeof(innolux_init_sequence_88));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_89, sizeof(innolux_init_sequence_89));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_90, sizeof(innolux_init_sequence_90));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_91, sizeof(innolux_init_sequence_91));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_92, sizeof(innolux_init_sequence_92));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_93, sizeof(innolux_init_sequence_93));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_94, sizeof(innolux_init_sequence_94));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_95, sizeof(innolux_init_sequence_95));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_96, sizeof(innolux_init_sequence_96));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_97, sizeof(innolux_init_sequence_97));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_98, sizeof(innolux_init_sequence_98));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_99, sizeof(innolux_init_sequence_99));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_100, sizeof(innolux_init_sequence_100));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_101, sizeof(innolux_init_sequence_101));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_102, sizeof(innolux_init_sequence_102));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_103, sizeof(innolux_init_sequence_103));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_104, sizeof(innolux_init_sequence_104));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_105, sizeof(innolux_init_sequence_105));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_106, sizeof(innolux_init_sequence_106));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_107, sizeof(innolux_init_sequence_107));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_108, sizeof(innolux_init_sequence_108));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_109, sizeof(innolux_init_sequence_109));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_110, sizeof(innolux_init_sequence_110));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_111, sizeof(innolux_init_sequence_111));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_112, sizeof(innolux_init_sequence_112));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_113, sizeof(innolux_init_sequence_113));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_114, sizeof(innolux_init_sequence_114));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_115, sizeof(innolux_init_sequence_115));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_116, sizeof(innolux_init_sequence_116));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_117, sizeof(innolux_init_sequence_117));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_118, sizeof(innolux_init_sequence_118));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_119, sizeof(innolux_init_sequence_119));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_120, sizeof(innolux_init_sequence_120));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_121, sizeof(innolux_init_sequence_121));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_122, sizeof(innolux_init_sequence_122));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_123, sizeof(innolux_init_sequence_123));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_124, sizeof(innolux_init_sequence_124));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_125, sizeof(innolux_init_sequence_125));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_126, sizeof(innolux_init_sequence_126));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_127, sizeof(innolux_init_sequence_127));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_128, sizeof(innolux_init_sequence_128));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_129, sizeof(innolux_init_sequence_129));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_130, sizeof(innolux_init_sequence_130));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_131, sizeof(innolux_init_sequence_131));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_132, sizeof(innolux_init_sequence_132));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_133, sizeof(innolux_init_sequence_133));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_134, sizeof(innolux_init_sequence_134));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_135, sizeof(innolux_init_sequence_135));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_136, sizeof(innolux_init_sequence_136));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_137, sizeof(innolux_init_sequence_137));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_138, sizeof(innolux_init_sequence_138));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_139, sizeof(innolux_init_sequence_139));
dsi_vc_dcs_write(intel_dsi, 0, innolux_init_sequence_140, sizeof(innolux_init_sequence_140));
}
static int dsi_mipi_430_cm_480_854_panel_enable(struct omap_dss_device *dssdev)
{
struct mapphone_data *map_data = (struct mapphone_data *) dssdev->data;
u8 data[7];
int ret;
DBG("dsi_mipi_430_cm_480_854_panel_enable() \n");
/* Exit sleep mode */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
/* 120ms delay for internal block stabilization */
msleep(120);
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* Enable 2 data lanes */
data[0] = EDISCO_CMD_DATA_LANE_CONFIG;
data[1] = EDISCO_CMD_DATA_LANE_TWO;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
msleep(10);
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF);
* D[1]=0 (Grama correction On);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = 0xb4;
data[1] = 0x0f;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* set page, column address */
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.x_res - 1) >> 8;
data[4] = (dssdev->panel.timings.x_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.y_res - 1) >> 8;
data[4] = (dssdev->panel.timings.y_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
mdelay(200);
if (atomic_cmpxchg(&map_data->state, PANEL_OFF, PANEL_ENABLED) ==
PANEL_OFF) {
DBG("panel enabled\n");
schedule_work(&map_data->work);
}
return 0;
error:
return -EINVAL;
}
static int s6e8aa0a01_write_block(struct omap_dss_device *dssdev,
const u8 *data, int len)
{
/* XXX: dsi_vc_dsc_write should take a const u8 */
return dsi_vc_dcs_write(dssdev, 1, (u8 *) data, len);
}
static int dsi_mipi_310_1_cm_320_480_panel_enable(
struct omap_dss_device *dssdev)
{
u8 data[7];
int ret;
DBG("dsi_mipi_310_1_cm_320_480_panel_enable() \n");
mdelay(15);
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret)
goto error;
mdelay(15);
/*Dimming function setting */
data[0] = 0x69;
data[1] = 0x00;
data[2] = 0xFF;
data[3] = 0x00;
data[4] = 0x14;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
/*Setting display brightness */
data[0] = 0x51;
data[1] = 0xFF;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
/*Setting CABC mode */
data[0] = 0x55;
data[1] = 0x02; /* 0x02 = On 0x00 = OFF */
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
/* setting CABC */
data[0] = 0x53;
data[1] = 0x16; /* Enable CABC. BCTRL=1, DD=1, BL=1*/
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
/* setting PWM */
data[0] = 0x6B;
data[1] = 0x00;
data[2] = 0x01; /* 0x01 = 31.26kHz */
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
if (ret)
goto error;
if (dssdev->ctrl.pixel_size == 16) {
/* setting pixel Format to 16 */
data[0] = 0x3A;
data[1] = 0x65;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
if (ret)
goto error;
dispc_enable_spatial_dithering(true);
}
return 0;
error:
return -EINVAL;
}
/* - In the LP mode, some panels have problems to receive command correctly
* so we will send command out and read it back to make sure the write
* command is accepted
* - if the dsi_vc_dcs_write() request, then we will not care about the
* write_dt (data type) */
static int mapphone_panel_lp_cmd_wrt_sync(bool dcs_cmd, int write_dt,
u8 *write_data, int write_len,
int read_cmd, int read_len,
int chk_val, int chk_mask)
{
int i, ret;
u8 data[7];
for (i = 0; i < DCS_CMD_RETRY_MAX; i++) {
if (dcs_cmd == true) {
ret = dsi_vc_dcs_write(EDISCO_CMD_VC,
write_data, write_len);
DBG("call dsi_vc_dcs_write"
"(len=0%d, p1/p2/p3/p4=0x%x/0x%x/0x%x/0x%x)\n",
write_len, write_data[0],
write_data[1], write_data[2], write_data[3]);
} else {
ret = dsi_vc_write(EDISCO_CMD_VC, write_dt,
write_data, write_len);
DBG("call dsi_vc_write"
"(dt=0x%x len=%d, p1/p2/p3/p4 = "
"0x%x/0x%x/0x%x/0x%x)\n",
write_dt, write_len, write_data[0],
write_data[1], write_data[2], write_data[3]);
}
if (ret) {
printk(KERN_ERR "failed to send cmd=0x%x \n",
write_data[0]);
continue;
}
mdelay(1);
/* TODO. Do not know how to handle and to check if more than
* 1 byte to read is requested*/
if (read_len < 0 || read_len > 1) {
printk(KERN_ERR "Invalid read_len=%d\n", read_len);
return -1;
}
/* Read the data back to make sure write_command is working */
data[0] = 0;
ret = dsi_vc_dcs_read(EDISCO_CMD_VC, read_cmd,
&data[0], read_len);
DBG("read_chk_cmd dcs_cmd=%d read_cmd=0x%x "
"read_len=%d chk_val=0x%x chk_mask=0x%x "
"read_val=0x%x \n",
dcs_cmd, read_cmd, read_len, chk_val,
chk_mask, data[0]);
if (ret < 0)
DBG("fail to read 0x%x cmd and "
"will try it again \n", read_cmd);
if ((data[0] & chk_mask) == chk_val) {
/* break if read back the same writing value*/
ret = 0;
break;
}
}
if (i >= DCS_CMD_RETRY_MAX) {
printk(KERN_ERR "failed to read dcs_cmd=%d read_cmd=0x%x "
"read_len=%d chk_val=0x%x chk_mask=0x%x\n"
"read_val=0x%x \n",
dcs_cmd, read_cmd, read_len, chk_val,
chk_mask, data[0]);
ret = -1;
}
return ret;
}
static int dsi_mipi_cm_480_854_panel_enable(struct omap_dss_device *dssdev)
{
struct mapphone_data *map_data = (struct mapphone_data *) dssdev->data;
u8 data[7];
int ret;
DBG("dsi_mipi_cm_480_854_panel_enable() \n");
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* enable lane setting and test registers*/
data[0] = 0xef;
data[1] = 0x01;
data[2] = 0x01;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 3);
/* 2nd param 61 = 1 line; 63 = 2 lanes */
data[0] = 0xef;
data[1] = 0x60;
data[2] = 0x63;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
/* 2nd param 0 = WVGA; 1 = WQVGA */
data[0] = 0xb3;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF);
* D[1]=0 (Grama correction On);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = 0xb4;
data[1] = 0x1f;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* set page, column address */
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.y_res - 1) >> 8;
data[4] = (dssdev->panel.timings.y_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.x_res - 1) >> 8;
data[4] = (dssdev->panel.timings.x_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
mdelay(200);
if (atomic_cmpxchg(&map_data->state, PANEL_OFF, PANEL_ENABLED) ==
PANEL_OFF) {
DBG("panel enabled\n");
schedule_work(&map_data->work);
}
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
static int sholes_panel_enable(struct omap_dss_device *dssdev)
{
u8 data[7];
int ret;
DBG("enable\n");
if (dssdev->platform_enable) {
ret = dssdev->platform_enable(dssdev);
if (ret)
return ret;
}
/* turn of mcs register acces protection */
data[0] = 0xb2;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* enable lane setting and test registers*/
data[0] = 0xef;
data[1] = 0x01;
data[2] = 0x01;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 3);
/* 2nd param 61 = 1 line; 63 = 2 lanes */
data[0] = 0xef;
data[1] = 0x60;
data[2] = 0x63;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
/* 2nd param 0 = WVGA; 1 = WQVGA */
data[0] = 0xb3;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF);
* D[1]=0 (Grama correction On);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = 0xb4;
data[1] = 0x1f;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* set page, column address */
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.y_res - 1) >> 8;
data[4] = (dssdev->panel.timings.y_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.x_res - 1) >> 8;
data[4] = (dssdev->panel.timings.x_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
/* turn it on */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
//ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_0, data, 1);
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
mdelay(200);
return 0;
error:
return -EINVAL;
}
static int dsi_mipi_310_2_cm_320_480_panel_enable(
struct omap_dss_device *dssdev)
{
u8 data[7];
int ret = 0;
DBG("dsi_mipi_310_2_cm_320_480_panel_enable \n");
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
data[0] = 0;
mdelay(10);
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
ret = dsi_vc_set_max_rx_packet_size(EDISCO_CMD_VC, 6);
if (ret)
printk(KERN_ERR "failed to set max_rx__packet_size\n");
memset(data, 0, sizeof(data));
ret = dsi_vc_dcs_read(EDISCO_CMD_VC, EDISCO_CMD_READ_DDB_START,
data, 6);
printk(KERN_INFO "Supplier id return=0x%x%x, "
"Manufacturer Version=0x%x%x, Revision=0x%x%x\n",
data[0], data[1], data[2], data[3],
data[4], data[5]);
dsi_vc_set_max_rx_packet_size(EDISCO_CMD_VC, 1);
data[0] = 0x3a;
if (dssdev->ctrl.pixel_size == 16)
data[1] = 0x05;
else if (dssdev->ctrl.pixel_size != 18)
data[1] = 0x06;
else {
printk(KERN_ERR "Invalied format pixel_size =%d\n",
dssdev->ctrl.pixel_size);
goto error;
}
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* Enable maximum brightness */
data[0] = 0x51;
data[1] = 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
memset(data, 0, sizeof(data));
/* Enable CABC Output */
data[0] = 0x53;
data[1] = 0x2c;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
static int dsi_mipi_280_vm_320_240_panel_enable(struct omap_dss_device *dssdev)
{
u8 data[10];
int ret;
DBG(" dsi_mipi_280_vm_320_240_panel_enable() \n");
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* Internal display set up */
data[0] = 0xC0;
data[1] = 0x11;
data[2] = 0x04;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 3);
/* Internal voltage set up */
data[0] = 0xD3;
data[1] = 0x1F;
data[2] = 0x01;
data[3] = 0x02;
data[4] = 0x15;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 5);
/* Internal voltage set up */
data[0] = 0xD4;
data[1] = 0x62;
data[2] = 0x1E;
data[3] = 0x00;
data[4] = 0xB7;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 5);
/* Internal display set up */
data[0] = 0xC5;
data[1] = 0x01;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* Load optimized red gamma (+) settings*/
data[0] = 0xE9;
data[1] = 0x01;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x0B;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized red gamma (-) settings*/
data[0] = 0xEA;
data[1] = 0x04;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x08;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized green gamma (+) settings*/
data[0] = 0xEB;
data[1] = 0x02;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x0B;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized green gamma (-) settings*/
data[0] = 0xEC;
data[1] = 0x05;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x08;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized blue gamma (+) settings*/
data[0] = 0xED;
data[1] = 0x04;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x0B;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized blue gamma (-) settings*/
data[0] = 0xEE;
data[1] = 0x07;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x08;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* turn on mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x03;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* turn it on */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret)
goto error;
mdelay(10);
data[0] = EDISCO_CMD_SET_DISPLAY_ON;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret) {
printk(KERN_ERR "failed to send EDISCO_CMD_SET_DISPLAY_ON \n");
goto error;
}
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
void bp080wx7_send_otp_cmds(struct intel_dsi_device *dsi)
{
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
DRM_DEBUG_KMS("\n");
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_01, sizeof(boe_init_sequence_01));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_02, sizeof(boe_init_sequence_02));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_03, sizeof(boe_init_sequence_03));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_04, sizeof(boe_init_sequence_04));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_05, sizeof(boe_init_sequence_05));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_06, sizeof(boe_init_sequence_06));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_07, sizeof(boe_init_sequence_07));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_08, sizeof(boe_init_sequence_08));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_09, sizeof(boe_init_sequence_09));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_10, sizeof(boe_init_sequence_10));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_11, sizeof(boe_init_sequence_11));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_12, sizeof(boe_init_sequence_12));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_13, sizeof(boe_init_sequence_13));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_14, sizeof(boe_init_sequence_14));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_15, sizeof(boe_init_sequence_15));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_16, sizeof(boe_init_sequence_16));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_17, sizeof(boe_init_sequence_17));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_18, sizeof(boe_init_sequence_18));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_19, sizeof(boe_init_sequence_19));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_20, sizeof(boe_init_sequence_20));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_21, sizeof(boe_init_sequence_21));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_22, sizeof(boe_init_sequence_22));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_23, sizeof(boe_init_sequence_23));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_24, sizeof(boe_init_sequence_24));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_25, sizeof(boe_init_sequence_25));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_26, sizeof(boe_init_sequence_26));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_27, sizeof(boe_init_sequence_27));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_28, sizeof(boe_init_sequence_28));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_29, sizeof(boe_init_sequence_29));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_30, sizeof(boe_init_sequence_30));
dsi_vc_dcs_write(intel_dsi, 0, boe_init_sequence_31, sizeof(boe_init_sequence_31));
}
