static int dpi_set_dsi_clk(enum omap_channel channel, unsigned long pck_req, unsigned long *fck, int *lck_div, int *pck_div) { struct dpi_clk_calc_ctx ctx; int r; bool ok; ok = dpi_dsi_clk_calc(pck_req, &ctx); if (!ok) return -EINVAL; r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo); if (r) return r; dss_select_lcd_clk_source(channel, dpi_get_alt_clk_src(channel)); dpi.mgr_config.clock_info = ctx.dispc_cinfo; *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk; *lck_div = ctx.dispc_cinfo.lck_div; *pck_div = ctx.dispc_cinfo.pck_div; return 0; }
static int dpi_set_dsi_clk(enum omap_channel channel, bool is_tft, unsigned long pck_req, unsigned long *pck) { struct dsi_clock_info dsi_cinfo; struct dispc_clock_info dispc_cinfo; int r; enum omap_dsi_index ix; DSSDBG("DPI clk source is DSI PLL\n"); ix = (channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2; if (!cpu_is_omap44xx()) { r = dsi_pll_calc_clock_div_pck(ix, is_tft, pck_req, &dsi_cinfo, &dispc_cinfo); if (r) return r; } else { dsi_cinfo.regn = 16; dsi_cinfo.regm = 115; dsi_cinfo.regm_dispc = 3; dsi_cinfo.regm_dsi = 3; dsi_cinfo.use_dss2_fck = true; r = dsi_calc_clock_rates(channel, &dsi_cinfo); DSSDBG("dpi_set_dsi_clk: dsi_calc_clock_rates=%d\n", r); if (r) return r; dispc_find_clk_divs(is_tft, pck_req, dsi_cinfo.dsi_pll_dispc_fclk, &dispc_cinfo); } r = dsi_pll_set_clock_div(ix, &dsi_cinfo); DSSDBG("dpi_set_dsi_clk: dsi_pll_set_clock_div=%d\n", r); if (r) return r; if (cpu_is_omap44xx()){ dss_select_dispc_clk_source(ix, (ix == DSI1) ? DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1); dss_select_lcd_clk_source(ix, (ix == DSI1) ? DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1); }else{ dss_select_dispc_clk_source(ix, DSS_SRC_DSI1_PLL_FCLK); } dispc_set_clock_div(channel, &dispc_cinfo); *pck = dispc_cinfo.pck; return 0; }
static void dpi_display_disable(struct omap_dss_device *dssdev) { struct omap_overlay_manager *mgr = dpi.output.manager; mutex_lock(&dpi.lock); dss_mgr_disable(mgr); if (dpi.dsidev) { dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); dsi_pll_uninit(dpi.dsidev, true); dsi_runtime_put(dpi.dsidev); } dispc_runtime_put(); if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) regulator_disable(dpi.vdds_dsi_reg); mutex_unlock(&dpi.lock); }
/* * linux/drivers/video/omap2/dss/dpi.c * * Copyright (C) 2009 Nokia Corporation * Author: Tomi Valkeinen <*****@*****.**> * * Some code and ideas taken from drivers/video/omap/ driver * by Imre Deak. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program. If not, see <http://www.gnu.org/licenses/>. */ #define DSS_SUBSYS_NAME "DPI" #include <linux/kernel.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <plat/display.h> #include <plat/cpu.h> #include <plat/omap-pm.h> #include "dss.h" static struct { struct regulator *vdds_dsi_reg; } dpi; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL static int dpi_set_dsi_clk(enum omap_channel channel, bool is_tft, unsigned long pck_req, unsigned long *pck) { struct dsi_clock_info dsi_cinfo; struct dispc_clock_info dispc_cinfo; int r; enum omap_dsi_index ix; DSSDBG("DPI clk source is DSI PLL\n"); ix = (channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2; if (!cpu_is_omap44xx()) { r = dsi_pll_calc_clock_div_pck(ix, is_tft, pck_req, &dsi_cinfo, &dispc_cinfo); if (r) return r; } else { dsi_cinfo.regn = 16; dsi_cinfo.regm = 115; dsi_cinfo.regm_dispc = 3; dsi_cinfo.regm_dsi = 3; dsi_cinfo.use_dss2_fck = true; r = dsi_calc_clock_rates(channel, &dsi_cinfo); DSSDBG("dpi_set_dsi_clk: dsi_calc_clock_rates=%d\n", r); if (r) return r; dispc_find_clk_divs(is_tft, pck_req, dsi_cinfo.dsi_pll_dispc_fclk, &dispc_cinfo); } r = dsi_pll_set_clock_div(ix, &dsi_cinfo); DSSDBG("dpi_set_dsi_clk: dsi_pll_set_clock_div=%d\n", r); if (r) return r; if (cpu_is_omap44xx()){ dss_select_dispc_clk_source(ix, (ix == DSI1) ? DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1); dss_select_lcd_clk_source(ix, (ix == DSI1) ? DSS_SRC_PLL1_CLK1 : DSS_SRC_PLL2_CLK1); }else{ dss_select_dispc_clk_source(ix, DSS_SRC_DSI1_PLL_FCLK); } dispc_set_clock_div(channel, &dispc_cinfo); *pck = dispc_cinfo.pck; return 0; } #else /* #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL */ static int dpi_set_dispc_clk(enum omap_channel channel, bool is_tft, unsigned long pck_req, unsigned long *pck) { struct dispc_clock_info dispc_cinfo; enum omap_dsi_index ix; DSSDBG("DPI clk source is DISPC\n"); ix = (channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2; if (cpu_is_omap44xx()) dispc_find_clk_divs(is_tft, pck_req, dss_clk_get_rate(DSS_CLK_FCK1), &dispc_cinfo); else { struct dss_clock_info dss_cinfo; int r; r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo); if (r) return r; r = dss_set_clock_div(&dss_cinfo); if (r) return r; } dss_select_dispc_clk_source(ix, DSS_SRC_DSS1_ALWON_FCLK); if (cpu_is_omap44xx()) dss_select_lcd_clk_source(ix, DSS_SRC_DSS1_ALWON_FCLK); dispc_set_clock_div(channel, &dispc_cinfo); *pck = dispc_cinfo.pck; return 0; }