static __init int brcm_populate_plat_regs(void) { int rc; const struct dt_device_node *node; u32 reg_base; u32 val; rc = brcm_get_dt_node("brcm,brcmstb-cpu-biu-ctrl", &node, ®_base); if ( rc ) return rc; if ( !dt_property_read_u32(node, "cpu-reset-config-reg", &val) ) { dprintk(XENLOG_ERR, "Missing property \"cpu-reset-config-reg\"\n"); return -ENOENT; } regs.hif_cpu_reset_config = reg_base + val; if ( !dt_property_read_u32(node, "cpu0-pwr-zone-ctrl-reg", &val) ) { dprintk(XENLOG_ERR, "Missing property \"cpu0-pwr-zone-ctrl-reg\"\n"); return -ENOENT; } regs.cpu0_pwr_zone_ctrl = reg_base + val; if ( !dt_property_read_u32(node, "scratch-reg", &val) ) { dprintk(XENLOG_ERR, "Missing property \"scratch-reg\"\n"); return -ENOENT; } regs.scratch_reg = reg_base + val; rc = brcm_get_dt_node("brcm,brcmstb-hif-continuation", NULL, ®_base); if ( rc ) return rc; regs.hif_boot_continuation = reg_base; dprintk(XENLOG_INFO, "hif_cpu_reset_config : %08xh\n", regs.hif_cpu_reset_config); dprintk(XENLOG_INFO, "cpu0_pwr_zone_ctrl : %08xh\n", regs.cpu0_pwr_zone_ctrl); dprintk(XENLOG_INFO, "hif_boot_continuation : %08xh\n", regs.hif_boot_continuation); dprintk(XENLOG_INFO, "scratch_reg : %08xh\n", regs.scratch_reg); return 0; }
int __init psci_init_0_1(void) { int ret; const struct dt_device_node *psci; psci = dt_find_compatible_node(NULL, NULL, "arm,psci"); if ( !psci ) return -EOPNOTSUPP; ret = psci_is_smc_method(psci); if ( ret ) return -EINVAL; if ( !dt_property_read_u32(psci, "cpu_on", &psci_cpu_on_nr) ) { printk("/psci node is missing the \"cpu_on\" property\n"); return -ENOENT; } psci_ver = PSCI_VERSION(0, 1); printk(XENLOG_INFO "Using PSCI-0.1 for SMP bringup\n"); return 0; }
/* Set up the timer on the boot CPU (early init function) */ void __init preinit_xen_time(void) { static const struct dt_device_match timer_ids[] __initconst = { DT_MATCH_TIMER, { /* sentinel */ }, }; int res; u32 rate; timer = dt_find_matching_node(NULL, timer_ids); if ( !timer ) panic("Unable to find a compatible timer in the device tree"); dt_device_set_used_by(timer, DOMID_XEN); res = platform_init_time(); if ( res ) panic("Timer: Cannot initialize platform timer"); res = dt_property_read_u32(timer, "clock-frequency", &rate); if ( res ) cpu_khz = rate / 1000; else cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; boot_count = READ_SYSREG64(CNTPCT_EL0); }
/* Set up the timer on the boot CPU */ int __init init_xen_time(void) { static const struct dt_device_match timer_ids[] __initconst = { DT_MATCH_TIMER, { /* sentinel */ }, }; struct dt_device_node *dev; int res; unsigned int i; u32 rate; dev = dt_find_matching_node(NULL, timer_ids); if ( !dev ) panic("Unable to find a compatible timer in the device tree"); dt_device_set_used_by(dev, DOMID_XEN); /* Retrieve all IRQs for the timer */ for ( i = TIMER_PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++ ) { res = platform_get_irq(dev, i); if ( res < 0 ) panic("Timer: Unable to retrieve IRQ %u from the device tree", i); timer_irq[i] = res; } printk("Generic Timer IRQ: phys=%u hyp=%u virt=%u\n", timer_irq[TIMER_PHYS_NONSECURE_PPI], timer_irq[TIMER_HYP_PPI], timer_irq[TIMER_VIRT_PPI]); res = platform_init_time(); if ( res ) panic("Timer: Cannot initialize platform timer"); /* Check that this CPU supports the Generic Timer interface */ if ( !cpu_has_gentimer ) panic("CPU does not support the Generic Timer v1 interface"); res = dt_property_read_u32(dev, "clock-frequency", &rate); if ( res ) cpu_khz = rate / 1000; else cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; boot_count = READ_SYSREG64(CNTPCT_EL0); printk("Using generic timer at %lu KHz\n", cpu_khz); return 0; }
/* Set up the timer on the boot CPU (early init function) */ static void __init preinit_dt_xen_time(void) { static const struct dt_device_match timer_ids[] __initconst = { DT_MATCH_TIMER, { /* sentinel */ }, }; int res; u32 rate; timer = dt_find_matching_node(NULL, timer_ids); if ( !timer ) panic("Unable to find a compatible timer in the device tree"); dt_device_set_used_by(timer, DOMID_XEN); res = dt_property_read_u32(timer, "clock-frequency", &rate); if ( res ) { cpu_khz = rate / 1000; timer_dt_clock_frequency = rate; } }
static int __init omap_uart_init(struct dt_device_node *dev, const void *data) { const char *config = data; struct omap_uart *uart; u32 clkspec; int res; u64 addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &omap_com; res = dt_property_read_u32(dev, "clock-frequency", &clkspec); if ( !res ) { printk("omap-uart: Unable to retrieve the clock frequency\n"); return -EINVAL; } uart->clock_hz = clkspec; uart->baud = 115200; uart->data_bits = 8; uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; res = dt_device_get_address(dev, 0, &addr, &size); if ( res ) { printk("omap-uart: Unable to retrieve the base" " address of the UART\n"); return res; } res = platform_get_irq(dev, 0); if ( res < 0 ) { printk("omap-uart: Unable to retrieve the IRQ\n"); return -EINVAL; } uart->irq = res; uart->regs = ioremap_nocache(addr, size); if ( !uart->regs ) { printk("omap-uart: Unable to map the UART memory\n"); return -ENOMEM; } uart->vuart.base_addr = addr; uart->vuart.size = size; uart->vuart.data_off = UART_THR; uart->vuart.status_off = UART_LSR << REG_SHIFT; uart->vuart.status = UART_LSR_THRE; /* Register with generic serial driver */ serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart); dt_device_set_used_by(dev, DOMID_XEN); return 0; }