/*
* writebackStage - determines when the pipeline should stop executing.
* also handles dump instructions
*
* Returns: TRUE when pipeline should stop
*/
bool writebackStage(forwardType * forward, statusType* status)
{
forward->W_dstE = W.dstE;
forward->W_valE = W.valE;
forward->W_dstM = W.dstM;
forward->W_valM = W.valM;
forward->W_icode = W.icode;
status->W_stat = W.stat;
if(W.stat == SAOK)
{
setRegister(W.dstE, W.valE);
setRegister(W.dstM, W.valM);
}
if(W.stat == SINS)
{
printf("Invalid instruction\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
return true;
}
else if(W.stat == SADR)
{
printf("Invalid memory address\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
return true;
}
else if(W.stat == SHLT)
{
return true;
}
if(W.icode == DUMP && W.valE & 1)
{
dumpProgramRegisters();
}
if(W.icode == DUMP && W.valE & 2)
{
dumpProcessorRegisters();
}
if(W.icode == DUMP && W.valE & 4)
{
dumpMemory();
}
return false;
}
/* Function Name: writebackStage
* Purpose: To simulate the writeback stage in a pipeline machine
*
* Parameters: forward - struct containing values used for forwarding
* status - struct containing values for the status of the memory and writeback stages
* Returns: TRUE if status is anything other than SAOK, FALSE otherwise
* Modifies: Appropriate values in forward and status structs
*/
bool writebackStage(forwardType *forward, statusType *status){
//set appropriate forwarding values
forward->W_valE = W.valE;
forward->W_dstE = W.dstE;
forward->W_dstM = W.dstM;
forward->W_valM = W.valM;
forward->W_icode = W.icode;
//set appropriate status value
status->W_stat = W.stat;
//check if instruction is a dump
if(W.icode == IDUMP){
if(W.valE & 0x1) dumpProgramRegisters();
if(W.valE & 0x2) dumpProcessorRegisters();
if(W.valE & 0x4) dumpMemory();
}
//only update registers if status is SAOK
if(W.stat == SAOK){
setRegister(W.dstE, W.valE);
setRegister(W.dstM, W.valM);
}
//determines next operation based on status
switch(W.stat){
case SAOK:
return FALSE; //continue program operation
case SHLT:
return TRUE; //program terminated due to halt
case SADR:
printf("Invalid memory address\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
return TRUE; //invalid memory address, dump everything and terminate
case SINS:
printf("Invalid instruction\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
return TRUE; //invalid instruction, dump everything and terminate
}
}
/**
* Execute the writeback stage.
* @param FORW A pointer to the forwarding struct `forwarding.h`
* @return True if processor should halt, otherwise false
*/
bool writebackStage(forwardType * FORW) {
FORW->W_dstE = W.dstE;
FORW->W_valE = W.valE;
FORW->W_icode = W.icode;
FORW->W_valM = W.valM;
FORW->W_dstM = W.dstM;
FORW->W_stat = W.stat;
if (W.stat == S_INS) {
printf("Invalid instruction\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
return true;
} else if (W.stat == S_ADR) {
printf("Invalid memory address\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
return true;
} else if (W.stat == S_HLT) {
return true;
} else {
// Status AOK
}
setRegister(W.dstE, W.valE);
setRegister(W.dstM, W.valM);
if (W.icode == I_DUMP) {
unsigned int dump_flags = getBits(0, 3, W.valE);
if (dump_flags & 0x1) {
dumpProgramRegisters();
}
if (dump_flags & 0x2) {
dumpProcessorRegisters();
}
if (dump_flags & 0x4) {
dumpMemory();
}
}
return false;
}
// Function: writebackStage
// Description: Simulates the writebackStage of the y86 pipe
// Params: *forward, *status
// Returns: Bool
// Modifies: None
bool writebackStage(forwardType *forward, statusType *status)
{
forward->W_dstE = W.dstE;
forward->W_valE = W.valE;
forward->W_valM = W.valM;
forward->W_dstM = W.dstM;
status->W_stat = W.stat;
forward->W_icode = W.icode;
//setRegister(W.dstE, W.valE);
//setRegister(W.dstM, W.valM);
/*if (W.icode == mrmovl || W.icode == popl)
{
setRegister(W.dstM, W.valM);
}
if(W.icode == OPL || W.icode == rrmovl || W.icode == irmovl || W.icode == popl || W.icode == pushl)
{
setRegister(W.dstE, W.valE);
}*/
if(W.dstM == none)
{
W.valM = 0;
}
if (W.stat == HLT || W.stat == INS || W.stat == ADR)
{
if(W.stat == INS)
{
printf("Invalid instruction\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
}
if(W.stat == ADR)
{
printf("Invalid memory address\n");
dumpProgramRegisters();
dumpProcessorRegisters();
dumpMemory();
}
return true;
}
else
{
setRegister(W.dstE, W.valE);
setRegister(W.dstM, W.valM);
if (W.icode == dump)
{
int temp_array[3] = {getBits(0,0,W.valE),getBits(1,1,W.valE),getBits(2,2,W.valE)};
if (temp_array[0])
{
dumpProgramRegisters();
}
if (temp_array[1])
{
dumpProcessorRegisters();
}
if (temp_array[2])
{
dumpMemory();
}
}
return false;
}
}
