static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) { struct dwc3_omap *omap = _omap; u32 reg; spin_lock(&omap->lock); reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1); if (reg & USBOTGSS_IRQ1_DMADISABLECLR) { dev_dbg(omap->dev, "DMA Disable was Cleared\n"); omap->dma_status = false; } if (reg & USBOTGSS_IRQ1_OEVT) dev_dbg(omap->dev, "OTG Event\n"); if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) dev_dbg(omap->dev, "DRVVBUS Rise\n"); if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) dev_dbg(omap->dev, "CHRGVBUS Rise\n"); if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) dev_dbg(omap->dev, "IDPULLUP Rise\n"); if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) dev_dbg(omap->dev, "DRVVBUS Fall\n"); if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) dev_dbg(omap->dev, "CHRGVBUS Fall\n"); if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) dev_dbg(omap->dev, "IDPULLUP Fall\n"); dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg); reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0); dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg); spin_unlock(&omap->lock); return IRQ_HANDLED; }
void dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status) { u32 val; struct dwc3_omap *omap = _omap; switch (status) { case OMAP_DWC3_ID_GROUND: dev_dbg(omap->dev, "ID GND\n"); val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | USBOTGSS_UTMI_OTG_STATUS_SESSEND); val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val); break; case OMAP_DWC3_VBUS_VALID: dev_dbg(omap->dev, "VBUS Connect\n"); val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | USBOTGSS_UTMI_OTG_STATUS_SESSVALID | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val); break; case OMAP_DWC3_ID_FLOAT: case OMAP_DWC3_VBUS_OFF: dev_dbg(omap->dev, "VBUS Disconnect\n"); val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND | USBOTGSS_UTMI_OTG_STATUS_IDDIG; dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val); break; default: dev_dbg(omap->dev, "ID float\n"); } return; }
static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) { u32 reg; reg = USBOTGSS_IRQO_COREIRQ_ST; dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg); reg = (USBOTGSS_IRQ1_OEVT | USBOTGSS_IRQ1_DRVVBUS_RISE | USBOTGSS_IRQ1_CHRGVBUS_RISE | USBOTGSS_IRQ1_DISCHRGVBUS_RISE | USBOTGSS_IRQ1_IDPULLUP_RISE | USBOTGSS_IRQ1_DRVVBUS_FALL | USBOTGSS_IRQ1_CHRGVBUS_FALL | USBOTGSS_IRQ1_DISCHRGVBUS_FALL | USBOTGSS_IRQ1_IDPULLUP_FALL); dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg); }
static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) { dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - omap->irq0_offset, value); }
static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) { dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + omap->irqmisc_offset, value); }
static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) { dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + omap->irqmisc_offset, value); }
static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) { dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + omap->utmi_otg_offset, value); }
static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) { dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + omap->utmi_otg_offset, value); }
static int __devinit dwc3_omap_probe(struct platform_device *pdev) { struct dwc3_omap_data *pdata = pdev->dev.platform_data; struct device_node *node = pdev->dev.of_node; struct platform_device *dwc3; struct dwc3_omap *omap; struct resource *res; struct device *dev = &pdev->dev; struct resource dwc3_res[2]; int devid; int size; int ret = -ENOMEM; int irq; const u32 *utmi_mode; u32 reg; void __iomem *base; void *context; omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); if (!omap) { dev_err(dev, "not enough memory\n"); return -ENOMEM; } platform_set_drvdata(pdev, omap); irq = platform_get_irq(pdev, 1); if (irq < 0) { dev_err(dev, "missing IRQ resource\n"); return -EINVAL; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(dev, "missing memory base resource\n"); return -EINVAL; } base = devm_ioremap_nocache(dev, res->start, resource_size(res)); if (!base) { dev_err(dev, "ioremap failed\n"); return -ENOMEM; } devid = dwc3_get_device_id(); if (devid < 0) return -ENODEV; omap->workqueue = create_singlethread_workqueue("omap_dwc3"); if (!omap->workqueue) { dev_err(dev, "unable to create workqueue for omap dwc3\n"); return -EINVAL; } dwc3 = platform_device_alloc("dwc3", devid); if (!dwc3) { dev_err(dev, "couldn't allocate dwc3 device\n"); goto err1; } context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL); if (!context) { dev_err(dev, "couldn't allocate dwc3 context memory\n"); goto err2; } spin_lock_init(&omap->lock); dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask); dwc3->dev.parent = dev; dwc3->dev.dma_mask = dev->dma_mask; dwc3->dev.dma_parms = dev->dma_parms; omap->resource_size = resource_size(res); omap->context = context; omap->dev = dev; omap->irq = irq; omap->base = base; omap->dwc3 = dwc3; omap->status = OMAP_DWC3_UNKNOWN; INIT_DELAYED_WORK(&omap->omap_dwc3_mailbox_work, omap_dwc3_mailbox_work); /* * REVISIT if we ever have two instances of the wrapper, we will be * in big trouble */ _omap = omap; pm_runtime_enable(dev); pm_runtime_get_sync(dev); reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); utmi_mode = of_get_property(node, "utmi-mode", &size); if (utmi_mode && size == sizeof(*utmi_mode)) { reg |= *utmi_mode; } else { if (!pdata) { dev_dbg(dev, "missing platform data\n"); } else { switch (pdata->utmi_mode) { case DWC3_OMAP_UTMI_MODE_SW: reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; break; case DWC3_OMAP_UTMI_MODE_HW: reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; break; default: dev_dbg(dev, "UNKNOWN utmi mode %d\n", pdata->utmi_mode); } } } dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg); /* check the DMA Status */ reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, "dwc3-omap", omap); if (ret) { dev_err(dev, "failed to request IRQ #%d --> %d\n", omap->irq, ret); goto err2; } dwc3_omap_enable_irqs(omap); pm_runtime_put_sync(dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) { dev_err(&pdev->dev, "missing memory base resource for dwc3\n"); ret = -EINVAL; goto err2; } memset(dwc3_res, 0, sizeof(dwc3_res)); dwc3_res[0].start = res->start; dwc3_res[0].end = res->end; dwc3_res[0].flags = res->flags; dwc3_res[0].name = res->name; irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "missing IRQ\n"); ret = -EINVAL; goto err2; } dwc3_res[1].start = irq; dwc3_res[1].flags = IORESOURCE_IRQ; dwc3_res[1].name = res->name; ret = platform_device_add_resources(dwc3, dwc3_res, ARRAY_SIZE(dwc3_res)); if (ret) { dev_err(dev, "couldn't add resources to dwc3 device\n"); goto err2; } ret = platform_device_add(dwc3); if (ret) { dev_err(dev, "failed to register dwc3 device\n"); goto err2; } pm_qos_add_request(&omap->pm_qos_request, PM_QOS_MEMORY_THROUGHPUT, PM_QOS_MEMORY_THROUGHPUT_DEFAULT_VALUE); wake_lock_init(&omap->dwc_wakelock, WAKE_LOCK_SUSPEND, "usb3_dwc"); return 0; err2: platform_device_put(dwc3); err1: dwc3_put_device_id(devid); return ret; }
static void omap_dwc3_set_mailbox(struct dwc3_omap *omap) { u32 val; u32 ret; struct platform_device *pdev = to_platform_device(&omap->dwc3->dev); struct dwc3 *dwc = platform_get_drvdata(pdev); switch (omap->status) { case OMAP_DWC3_ID_GROUND: dev_dbg(omap->dev, "ID GND\n"); dwc3_core_host_init(&omap->dwc3->dev); ret = pm_runtime_get_sync(omap->dev); if (ret < 0) { dev_err(omap->dev, "get_sync failed with err %d\n", ret); return; } val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | USBOTGSS_UTMI_OTG_STATUS_SESSEND); val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val); pm_qos_update_request(&omap->pm_qos_request, PM_QOS_MEMORY_THROUGHPUT_USB3); pm_runtime_put_sync(omap->dev); break; case OMAP_DWC3_VBUS_VALID: dev_dbg(omap->dev, "VBUS Connect\n"); dwc3_core_late_init(&omap->dwc3->dev); ret = pm_runtime_get_sync(omap->dev); if (ret < 0) { dev_err(omap->dev, "get_sync failed with err %d\n", ret); return; } val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | USBOTGSS_UTMI_OTG_STATUS_SESSVALID | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val); pm_qos_update_request(&omap->pm_qos_request, PM_QOS_MEMORY_THROUGHPUT_USB3); pm_runtime_put_sync(omap->dev); break; case OMAP_DWC3_ID_FLOAT: case OMAP_DWC3_VBUS_OFF: dev_dbg(omap->dev, "VBUS Disconnect\n"); dwc->is_connected = false; dwc->gadget_is_connected = false; pm_qos_update_request(&omap->pm_qos_request, PM_QOS_DEFAULT_VALUE); ret = pm_runtime_get_sync(omap->dev); if (ret < 0) { dev_err(omap->dev, "get_sync failed with err %d\n", ret); return; } val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND | USBOTGSS_UTMI_OTG_STATUS_IDDIG; dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val); pm_runtime_put_sync(omap->dev); /* * Give enough time for the DWC core to process disconnect * interrupt after mailboxing for the disconnect event is * done, before shutting down the DWC core. */ msleep(25); if (omap->status == OMAP_DWC3_ID_FLOAT) dwc3_host_exit(dwc); dwc3_core_shutdown(&omap->dwc3->dev); wake_unlock(&omap->dwc_wakelock); break; default: dev_dbg(omap->dev, "ID float\n"); } return; }
static int dwc3_omap_probe(struct platform_device *pdev) { struct dwc3_omap_data *pdata = pdev->dev.platform_data; struct device_node *node = pdev->dev.of_node; struct dwc3_omap *omap; struct resource *res; struct device *dev = &pdev->dev; int size; int ret = -ENOMEM; int irq; const u32 *utmi_mode; u32 reg; void __iomem *base; void *context; omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); if (!omap) { dev_err(dev, "not enough memory\n"); return -ENOMEM; } platform_set_drvdata(pdev, omap); irq = platform_get_irq(pdev, 1); if (irq < 0) { dev_err(dev, "missing IRQ resource\n"); return -EINVAL; } res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!res) { dev_err(dev, "missing memory base resource\n"); return -EINVAL; } base = devm_ioremap_nocache(dev, res->start, resource_size(res)); if (!base) { dev_err(dev, "ioremap failed\n"); return -ENOMEM; } ret = dwc3_omap_register_phys(omap); if (ret) { dev_err(dev, "couldn't register PHYs\n"); return ret; } context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL); if (!context) { dev_err(dev, "couldn't allocate dwc3 context memory\n"); return -ENOMEM; } spin_lock_init(&omap->lock); omap->resource_size = resource_size(res); omap->context = context; omap->dev = dev; omap->irq = irq; omap->base = base; /* * REVISIT if we ever have two instances of the wrapper, we will be * in big trouble */ _omap = omap; pm_runtime_enable(dev); ret = pm_runtime_get_sync(dev); if (ret < 0) { dev_err(dev, "get_sync failed with err %d\n", ret); return ret; } reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); utmi_mode = of_get_property(node, "utmi-mode", &size); if (utmi_mode && size == sizeof(*utmi_mode)) { reg |= *utmi_mode; } else { if (!pdata) { dev_dbg(dev, "missing platform data\n"); } else { switch (pdata->utmi_mode) { case DWC3_OMAP_UTMI_MODE_SW: reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; break; case DWC3_OMAP_UTMI_MODE_HW: reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; break; default: dev_dbg(dev, "UNKNOWN utmi mode %d\n", pdata->utmi_mode); } } } dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg); /* check the DMA Status */ reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, "dwc3-omap", omap); if (ret) { dev_err(dev, "failed to request IRQ #%d --> %d\n", omap->irq, ret); return ret; } /* enable all IRQs */ reg = USBOTGSS_IRQO_COREIRQ_ST; dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg); reg = (USBOTGSS_IRQ1_OEVT | USBOTGSS_IRQ1_DRVVBUS_RISE | USBOTGSS_IRQ1_CHRGVBUS_RISE | USBOTGSS_IRQ1_DISCHRGVBUS_RISE | USBOTGSS_IRQ1_IDPULLUP_RISE | USBOTGSS_IRQ1_DRVVBUS_FALL | USBOTGSS_IRQ1_CHRGVBUS_FALL | USBOTGSS_IRQ1_DISCHRGVBUS_FALL | USBOTGSS_IRQ1_IDPULLUP_FALL); dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg); if (node) { ret = of_platform_populate(node, NULL, NULL, dev); if (ret) { dev_err(&pdev->dev, "failed to add create dwc3 core\n"); return ret; } } return 0; }