/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
void c_entry(void)
{
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Setup miscellaneous board functions */
ea3250_board_init();
/* enable interupts */
enable_irq();
uart_output_init();
if (TRUE == ethIf_init(mac)) {
uart_output("MAC initialized\r\n");
}
else {
uart_output("Failed to initialized MAC controller\r\n");
}
while(1)
{
UNS_16 len = 0;
len = ethIf_poll(inBuf, INBUF_LEN);
if(len > 0)
{
ethInput(inBuf, len);
}
}
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
TMR_PSCALE_SETUP_T pscale;
TMR_MATCH_SETUP_T msetup;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Setup miscellaneous board functions */
ea3250_board_init();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install timer interrupts handlers as a IRQ interrupts */
int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt);
int_install_irq_handler(IRQ_TIMER1, (PFV) timer1_user_interrupt);
/* Open timers - this will enable the clocks for all timers when
match control, match output, and capture control functions
disabled. Default clock will be internal. */
timer0dev = timer_open(TIMER_CNTR0, 0);
timer1dev = timer_open(TIMER_CNTR1, 0);
/******************************************************************/
/* Setup timer 0 for a 1Hz match rate */
/* Use a prescale count time of 100uS */
pscale.ps_tick_val = 0; /* Use ps_us_val value */
pscale.ps_us_val = 100; /* 100uS */
timer_ioctl(timer0dev, TMR_SETUP_PSCALE, (INT_32) &pscale);
/* Use a match count value of 10000 (10000 * 100uS = 1000mS (1Hz)) */
msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */
msetup.use_match_int = TRUE; /* Generate match interrupt on match */
msetup.stop_on_match = FALSE; /* Do not stop timer on match */
msetup.reset_on_match = TRUE; /* Reset timer counter on match */
msetup.match_tick_val = 9999; /* Match is when timer count is 10000 */
timer_ioctl(timer0dev, TMR_SETUP_MATCH, (INT_32) &msetup);
/* Clear any latched timer 0 interrupts and enable match
interrupt */
timer_ioctl(timer0dev, TMR_CLEAR_INTS,
(TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) |
TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) |
TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) |
TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3)));
/******************************************************************/
/******************************************************************/
/* Setup timer 1 for a 4.9Hz match rate */
/* Use a prescale count time of 100uS */
pscale.ps_tick_val = 0; /* Use ps_us_val value */
pscale.ps_us_val = 10; /* 100uS */
timer_ioctl(timer1dev, TMR_SETUP_PSCALE, (INT_32) &pscale);
/* Use a match value of 490 (490 * 100uS) */
msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */
msetup.use_match_int = TRUE; /* Generate match interrupt on match */
msetup.stop_on_match = FALSE; /* Do not stop timer on match */
msetup.reset_on_match = TRUE; /* Reset timer counter on match */
msetup.match_tick_val = 489;
timer_ioctl(timer1dev, TMR_SETUP_MATCH, (INT_32) &msetup);
/* Clear any latched timer 1 interrupts and enable match
interrupt */
timer_ioctl(timer1dev, TMR_CLEAR_INTS,
(TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) |
TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) |
TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) |
TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3)));
/******************************************************************/
/* Enable timers (starts counting) */
msecs = 0;
timer_ioctl(timer0dev, TMR_ENABLE, 1);
timer_ioctl(timer1dev, TMR_ENABLE, 1);
/* Enable timer interrupts in the interrupt controller */
int_enable(IRQ_TIMER0);
int_enable(IRQ_TIMER1);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 20 seconds and let interrupts toggle the LEDs */
while (msecs < (10 * 1000));
/* Disable timer interrupts in the interrupt controller */
int_disable(IRQ_TIMER0);
int_disable(IRQ_TIMER1);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Close timers */
timer_close(timer0dev);
timer_close(timer1dev);
return 1;
}
void c_entry(void)
{
static I2C_SETUP_T i2c_setup[2];
static volatile I2C_MTX_SETUP_T i2c_mtx_setup;
static I2C_MTXRX_SETUP_T i2c_mtxrx_setup;
static I2C_MRX_SETUP_T i2c_mrx_setup;
UNS_8 rx_data[16], tx_data[16];
/* Disable interrupts in ARM core */
disable_irq();
/* Setup miscellaneous board functions */
ea3250_board_init();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Enable I2C1/2 clock */
clkpwr_clk_en_dis(CLKPWR_I2C1_CLK,1);
clkpwr_clk_en_dis(CLKPWR_I2C2_CLK,1);
/* install default I2C1 & I2C2 interrupt handlers */
int_install_ext_irq_handler(IRQ_I2C_1,
(PFV) i2c1_user_interrupt, ACTIVE_LOW, 1);
int_install_ext_irq_handler(IRQ_I2C_2,
(PFV) i2c2_user_interrupt, ACTIVE_LOW, 1);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* open I2C1 */
i2cdev1 = i2c_open(I2C1, 0);
/* formally assign a 7-bit slave address 0x50 to I2C1 */
/* I2C1 clock is 100 kHz, 50% duty cycle, high pin drive */
i2c_setup[0].addr_mode = ADDR7BIT;
// i2c_setup[0].sl_addr = 0x60;
i2c_setup[0].rate_option= I2C_RATE_RELATIVE;
i2c_setup[0].rate = 100000;
i2c_setup[0].low_phase = 50;
i2c_setup[0].high_phase = 50;
i2c_setup[0].pins_drive = I2C_PINS_HIGH_DRIVE;
i2c_ioctl((UNS_32) i2cdev1, I2C_SETUP, (UNS_32) &i2c_setup[0]);
/* Write 9 bytes to PCA9532 and init registers, starting with reg 0x02 + auto increment = 0x10 */
tx_data[0] = 0x12;
tx_data[1] = 151; /*PSC0 = blink 1s*/
tx_data[2] = 256/3; /*PWM0 1/3 duty cycle*/
tx_data[3] = 0; /*PSC1 = blink 1/152s*/
tx_data[4] = 256/32;/*PWM1 = 1/32 duty cycle*/
tx_data[5] = 0x00; /*LS0 outputs 0 - 3 High impedance*/
tx_data[6] = 0x00; /*LS1 outputs 4 - 7 High impedance*/
tx_data[7] = 0xE4; /*LS2 output 8 High impedance (LED1 OFF)
output 9 LOW (LED2 ON)
output 10 blinks at PWM0 rate
output 11 blinks at PWM1 rate*/
tx_data[8] = 0xE4; /*LS2 output 12 High impedance (LED1 OFF)
output 13 LOW (LED2 ON)
output 14 blinks at PWM0 rate
output 15 blinks at PWM1 rate*/
i2c_mtx_setup.addr_mode = ADDR7BIT;
i2c_mtx_setup.sl_addr = 0x60;
i2c_mtx_setup.tx_data = &tx_data[0];
i2c_mtx_setup.tx_length = 9;
i2c_mtx_setup.retransmissions_max = 10;
i2c_ioctl(i2cdev1, I2C_MASTER_TX, (INT_32)&i2c_mtx_setup);
while (( i2c_mtx_setup.status & I2C_SETUP_STATUS_DONE) == 0 /*&& mtx_irq < 100000*/);
i2c_close(i2cdev1);
}
