void sg8100_cardbus_fixup(struct pci_controller *hose, int current_bus, int pci_devfn) { unsigned long ba; unsigned int scr, mfr; unsigned short bcr; unsigned char dc; /* Leave the cardbus slots in the reset state for now */ bcr = 0x0340; early_write_config_word(hose, current_bus, pci_devfn, 0x3e, bcr); /* Set to use serialized interrupts - the power on default */ dc = 0x66; early_write_config_byte(hose, current_bus, pci_devfn, 0x92, dc); /* Enable MFUNC0 to be interrupt source for slot */ scr = 0x28449060; early_write_config_dword(hose, current_bus, pci_devfn, 0x80, scr); mfr = 0x00001002; early_write_config_dword(hose, current_bus, pci_devfn, 0x8c, mfr); /* Turn of power to cardbus slot */ ba = 0; early_read_config_dword(hose, current_bus, pci_devfn, PCI_BASE_ADDRESS_0, &ba); if (ba) { /* Request power off on cardbus slot */ writel(0, ba+0x4); /* MASK */ writel(0, ba+0x10); /* CONTROL */ } }
/** * xilinx_early_pci_scan - List pci config space for available devices * * List pci devices in very early phase. */ void __init xilinx_early_pci_scan(struct pci_controller *hose) { u32 bus = 0; u32 val, dev, func, offset; /* Currently we have only 2 device connected - up-to 32 devices */ for (dev = 0; dev < 2; dev++) { /* List only first function number - up-to 8 functions */ for (func = 0; func < 1; func++) { printk(KERN_INFO "%02x:%02x:%02x", bus, dev, func); /* read the first 64 standardized bytes */ /* Up-to 192 bytes can be list of capabilities */ for (offset = 0; offset < 64; offset += 4) { early_read_config_dword(hose, bus, PCI_DEVFN(dev, func), offset, &val); if (offset == 0 && val == 0xFFFFFFFF) { printk(KERN_CONT "\nABSENT"); break; } if (!(offset % 0x10)) printk(KERN_CONT "\n%04x: ", offset); printk(KERN_CONT "%08x ", val); } printk(KERN_INFO "\n"); } } }
static void __init yosemite_setup_hose(void) { unsigned int bar_response, bar; struct pci_controller *hose; yosemite_setup_pci(); hose = pcibios_alloc_controller(); if (!hose) return; hose->first_busno = 0; hose->last_busno = 0xff; hose->pci_mem_offset = YOSEMITE_PCI_MEM_OFFSET; pci_init_resource(&hose->io_resource, YOSEMITE_PCI_LOWER_IO, YOSEMITE_PCI_UPPER_IO, IORESOURCE_IO, "PCI host bridge"); pci_init_resource(&hose->mem_resources[0], YOSEMITE_PCI_LOWER_MEM, YOSEMITE_PCI_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge"); ppc_md.pci_exclude_device = yosemite_exclude_device; hose->io_space.start = YOSEMITE_PCI_LOWER_IO; hose->io_space.end = YOSEMITE_PCI_UPPER_IO; hose->mem_space.start = YOSEMITE_PCI_LOWER_MEM; hose->mem_space.end = YOSEMITE_PCI_UPPER_MEM; isa_io_base = (unsigned long)ioremap64(YOSEMITE_PCI_IO_BASE, YOSEMITE_PCI_IO_SIZE); hose->io_base_virt = (void *)isa_io_base; setup_indirect_pci(hose, YOSEMITE_PCI_CFGA_PLB32, YOSEMITE_PCI_CFGD_PLB32); hose->set_cfg_type = 1; /* Zero config bars */ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { early_write_config_dword(hose, hose->first_busno, PCI_FUNC(hose->first_busno), bar, 0x00000000); early_read_config_dword(hose, hose->first_busno, PCI_FUNC(hose->first_busno), bar, &bar_response); } hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = yosemite_map_irq; }
static int __init mvme5100_add_bridge(struct device_node *dev) { const int *bus_range; int len; struct pci_controller *hose; unsigned short devid; pr_info("Adding PCI host bridge %s\n", dev->full_name); bus_range = of_get_property(dev, "bus-range", &len); hose = pcibios_alloc_controller(dev); if (hose == NULL) return -ENOMEM; hose->first_busno = bus_range ? bus_range[0] : 0; hose->last_busno = bus_range ? bus_range[1] : 0xff; setup_indirect_pci(hose, 0xfe000cf8, 0xfe000cfc, 0); pci_process_bridge_OF_ranges(hose, dev, 1); early_read_config_word(hose, 0, 0, PCI_DEVICE_ID, &devid); if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) { pr_err("HAWK PHB not present?\n"); return 0; } early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase); if (pci_membase == 0) { pr_err("HAWK PHB mibar not correctly set?\n"); return 0; } pr_info("mvme5100_pic_init: pci_membase: %x\n", pci_membase); return 0; }
int __init pcore_find_bridges(void) { struct pci_controller* hose; int host_bridge, board_type; hose = pcibios_alloc_controller(); if (!hose) return 0; mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B, MPC10X_MAPB_EUMB_BASE); /* Determine board type */ early_read_config_dword(hose, 0, PCI_DEVFN(0,0), PCI_VENDOR_ID, &host_bridge); if (host_bridge == MPC10X_BRIDGE_106) board_type = PCORE_TYPE_6750; else /* MPC10X_BRIDGE_107 */ board_type = PCORE_TYPE_680; hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); ppc_md.pcibios_fixup = pcore_pcibios_fixup; ppc_md.pci_swizzle = common_swizzle; if (board_type == PCORE_TYPE_6750) ppc_md.pci_map_irq = pcore_6750_map_irq; else /* PCORE_TYPE_680 */ ppc_md.pci_map_irq = pcore_680_map_irq; return board_type; }
static void __init katana_setup_bridge(void) { struct pci_controller hose; struct mv64x60_setup_info si; void __iomem *vaddr; int i; u32 v; u16 val, type; u8 save_exclude; /* * Some versions of the Katana firmware mistakenly change the vendor * & device id fields in the bridge's pci device (visible via pci * config accesses). This breaks mv64x60_init() because those values * are used to identify the type of bridge that's there. Artesyn * claims that the subsystem vendor/device id's will have the correct * Marvell values so this code puts back the correct values from there. */ memset(&hose, 0, sizeof(hose)); vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE); setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR, vaddr + MV64x60_PCI0_CONFIG_DATA); save_exclude = mv64x60_pci_exclude_bridge; mv64x60_pci_exclude_bridge = 0; early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val); if (val != PCI_VENDOR_ID_MARVELL) { early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_SUBSYSTEM_VENDOR_ID, &val); early_write_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, val); early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_SUBSYSTEM_ID, &val); early_write_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, val); } /* * While we're in here, set the hotswap register correctly. * Turn off blue LED; mask ENUM#, clear insertion & extraction bits. */ early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0), MV64360_PCICFG_CPCI_HOTSWAP, &v); v &= ~(1<<19); v |= ((1<<17) | (1<<22) | (1<<23)); early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0), MV64360_PCICFG_CPCI_HOTSWAP, v); /* While we're at it, grab the bridge type for later */ early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type); mv64x60_pci_exclude_bridge = save_exclude; iounmap(vaddr); memset(&si, 0, sizeof(si)); si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; si.pci_1.enable_bus = 1; si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR; si.pci_1.pci_io.pci_base_hi = 0; si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR; si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE; si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR; si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR; si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR; si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE; si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; si.pci_1.pci_cmd_bits = 0; si.pci_1.latency_timer = 0x80; for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { #if defined(CONFIG_NOT_COHERENT_CACHE) si.cpu_prot_options[i] = 0; si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; si.pci_1.acc_cntl_options[i] = MV64360_PCI_ACC_CNTL_SNOOP_NONE | MV64360_PCI_ACC_CNTL_SWAP_NONE | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; #else si.cpu_prot_options[i] = 0; si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; si.pci_1.acc_cntl_options[i] = MV64360_PCI_ACC_CNTL_SNOOP_WB | MV64360_PCI_ACC_CNTL_SWAP_NONE | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | ((type == PCI_DEVICE_ID_MARVELL_MV64360) ? MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES : MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES); #endif } /* Lookup PCI host bridges */ if (mv64x60_init(&bh, &si)) printk(KERN_WARNING "Bridge initialization failed.\n"); pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = katana_map_irq; ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; mv64x60_set_bus(&bh, 1, 0); bh.hose_b->first_busno = 0; bh.hose_b->last_busno = 0xff; /* * Need to access hotswap reg which is in the pci config area of the * bridge's hose 0. Note that pcibios_alloc_controller() can't be used * to alloc hose_a b/c that would make hose 0 known to the generic * pci code which we don't want. */ bh.hose_a = &katana_hose_a; setup_indirect_pci_nomap(bh.hose_a, bh.v_base + MV64x60_PCI0_CONFIG_ADDR, bh.v_base + MV64x60_PCI0_CONFIG_DATA); }
void __init bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) { #ifdef CONFIG_PCI unsigned int bar_response, bar; /* * Expected PCI mapping: * * PLB addr PCI memory addr * --------------------- --------------------- * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff * * PLB addr PCI io addr * --------------------- --------------------- * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 * * The following code is simplified by assuming that the bootrom * has been well behaved in following this mapping. */ #ifdef DEBUG int i; printk("ioremap PCLIO_BASE = 0x%x\n", pcip); printk("PCI bridge regs before fixup \n"); for (i = 0; i <= 3; i++) { printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); } printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); #endif /* added for IBM boot rom version 1.15 bios bar changes -AK */ /* Disable region first */ out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); /* PLB starting addr, PCI: 0x80000000 */ out_le32((void *) &(pcip->pmm[0].la), 0x80000000); /* PCI start addr, 0x80000000 */ out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); /* 512MB range of PLB to PCI */ out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); /* Enable no pre-fetch, enable region */ out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - (PPC405_PCI_UPPER_MEM - PPC405_PCI_MEM_BASE)) | 0x01)); /* Disable region one */ out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); out_le32((void *) &(pcip->pmm[1].la), 0x00000000); out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); out_le32((void *) &(pcip->ptm1ms), 0x00000001); /* Disable region two */ out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); out_le32((void *) &(pcip->pmm[2].la), 0x00000000); out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); out_le32((void *) &(pcip->ptm2ms), 0x00000000); out_le32((void *) &(pcip->ptm2la), 0x00000000); /* Zero config bars */ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { early_write_config_dword(hose, hose->first_busno, PCI_FUNC(hose->first_busno), bar, 0x00000000); early_read_config_dword(hose, hose->first_busno, PCI_FUNC(hose->first_busno), bar, &bar_response); DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", hose->first_busno, PCI_SLOT(hose->first_busno), PCI_FUNC(hose->first_busno), bar, bar_response); } /* end work arround */ #ifdef DEBUG printk("PCI bridge regs after fixup \n"); for (i = 0; i <= 3; i++) { printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); } printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); #endif #endif }
static int __init tx4927_pcibios_init(void) { unsigned int id; u32 pci_devfn; int devfn_start = 0; int devfn_stop = 0xff; int busno = 0; /* One bus on the Toshiba */ struct pci_controller *hose = &tx4927_controller; TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, "-\n"); for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { early_read_config_dword(hose, busno, busno, pci_devfn, PCI_VENDOR_ID, &id); if (id == 0xffffffff) { continue; } if (id == 0x94601055) { u8 v08_64; u32 v32_b0; u8 v08_e1; #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG char *s = " sb/isa --"; #endif TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", s); early_read_config_byte(hose, busno, busno, pci_devfn, 0x64, &v08_64); early_read_config_dword(hose, busno, busno, pci_devfn, 0xb0, &v32_b0); early_read_config_byte(hose, busno, busno, pci_devfn, 0xe1, &v08_e1); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0x64 = 0x%02x\n", s, v08_64); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0xb0 = 0x%02x\n", s, v32_b0); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0xe1 = 0x%02x\n", s, v08_e1); /* serial irq control */ v08_64 = 0xd0; /* serial irq pin */ v32_b0 |= 0x00010000; /* ide irq on isa14 */ v08_e1 &= 0xf0; v08_e1 |= 0x0d; TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0x64 = 0x%02x\n", s, v08_64); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0xb0 = 0x%02x\n", s, v32_b0); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0xe1 = 0x%02x\n", s, v08_e1); early_write_config_byte(hose, busno, busno, pci_devfn, 0x64, v08_64); early_write_config_dword(hose, busno, busno, pci_devfn, 0xb0, v32_b0); early_write_config_byte(hose, busno, busno, pci_devfn, 0xe1, v08_e1); #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG { early_read_config_byte(hose, busno, busno, pci_devfn, 0x64, &v08_64); early_read_config_dword(hose, busno, busno, pci_devfn, 0xb0, &v32_b0); early_read_config_byte(hose, busno, busno, pci_devfn, 0xe1, &v08_e1); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0x64 = 0x%02x\n", s, v08_64); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0xb0 = 0x%02x\n", s, v32_b0); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0xe1 = 0x%02x\n", s, v08_e1); } #endif TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", s); } if (id == 0x91301055) { u8 v08_04; u8 v08_09; u8 v08_41; u8 v08_43; u8 v08_5c; #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG char *s = " sb/ide --"; #endif TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", s); early_read_config_byte(hose, busno, busno, pci_devfn, 0x04, &v08_04); early_read_config_byte(hose, busno, busno, pci_devfn, 0x09, &v08_09); early_read_config_byte(hose, busno, busno, pci_devfn, 0x41, &v08_41); early_read_config_byte(hose, busno, busno, pci_devfn, 0x43, &v08_43); early_read_config_byte(hose, busno, busno, pci_devfn, 0x5c, &v08_5c); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0x04 = 0x%02x\n", s, v08_04); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0x09 = 0x%02x\n", s, v08_09); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0x41 = 0x%02x\n", s, v08_41); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0x43 = 0x%02x\n", s, v08_43); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg 0x5c = 0x%02x\n", s, v08_5c); /* enable ide master/io */ v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); /* enable ide native mode */ v08_09 |= 0x05; /* enable primary ide */ v08_41 |= 0x80; /* enable secondary ide */ v08_43 |= 0x80; /* * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! * * This line of code is intended to provide the user with a work * around solution to the anomalies cited in SMSC's anomaly sheet * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". * * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! */ v08_5c |= 0x01; TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0x04 = 0x%02x\n", s, v08_04); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0x09 = 0x%02x\n", s, v08_09); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0x41 = 0x%02x\n", s, v08_41); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0x43 = 0x%02x\n", s, v08_43); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s mid 0x5c = 0x%02x\n", s, v08_5c); early_write_config_byte(hose, busno, busno, pci_devfn, 0x5c, v08_5c); early_write_config_byte(hose, busno, busno, pci_devfn, 0x04, v08_04); early_write_config_byte(hose, busno, busno, pci_devfn, 0x09, v08_09); early_write_config_byte(hose, busno, busno, pci_devfn, 0x41, v08_41); early_write_config_byte(hose, busno, busno, pci_devfn, 0x43, v08_43); #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG { early_read_config_byte(hose, busno, busno, pci_devfn, 0x04, &v08_04); early_read_config_byte(hose, busno, busno, pci_devfn, 0x09, &v08_09); early_read_config_byte(hose, busno, busno, pci_devfn, 0x41, &v08_41); early_read_config_byte(hose, busno, busno, pci_devfn, 0x43, &v08_43); early_read_config_byte(hose, busno, busno, pci_devfn, 0x5c, &v08_5c); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0x04 = 0x%02x\n", s, v08_04); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0x09 = 0x%02x\n", s, v08_09); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0x41 = 0x%02x\n", s, v08_41); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0x43 = 0x%02x\n", s, v08_43); TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end 0x5c = 0x%02x\n", s, v08_5c); } #endif TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", s); } } register_pci_controller(&tx4927_controller); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, "+\n"); return 0; }
int __init raven_init(void) { unsigned int devid; unsigned int pci_membase; unsigned char base_mod; /* Check to see if the Raven chip exists. */ if ( _prep_type != _PREP_Motorola) { OpenPIC_Addr = NULL; return 0; } /* Check to see if this board is a type that might have a Raven. */ if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) { OpenPIC_Addr = NULL; return 0; } /* Check the first PCI device to see if it is a Raven. */ early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &devid); switch (devid & 0xffff0000) { case MPIC_RAVEN_ID: MotMPIC = MOT_RAVEN_PRESENT; break; case MPIC_HAWK_ID: MotMPIC = MOT_HAWK_PRESENT; break; default: OpenPIC_Addr = NULL; return 0; } /* Read the memory base register. */ early_read_config_dword(NULL, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase); if (pci_membase == 0) { OpenPIC_Addr = NULL; return 0; } /* Map the Raven MPIC registers to virtual memory. */ OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000); OpenPIC_InitSenses = prep_openpic_initsenses; OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); ppc_md.get_irq = openpic_get_irq; /* If raven is present on Motorola store the system config register * for later use. */ ProcInfo = (unsigned long *)ioremap(0xfef80400, 4); /* Indicate to system if this is a multiprocessor board */ if (!(*ProcInfo & MOT_PROC2_BIT)) { mot_multi = 1; } /* This is a hack. If this is a 2300 or 2400 mot board then there is * no keyboard controller and we have to indicate that. */ base_mod = inb(MOTOROLA_BASETYPE_REG); if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1)) prep_keybd_present = 0; return 1; }